- 27 Nov, 2017 5 commits
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Felix Kuehling authored
This commit adds several debugfs entries for kfd: kfd/hqds: dumps all HQDs on all GPUs for KFD-controlled compute and SDMA RLC queues kfd/mqds: dumps all MQDs of all KFD processes on all GPUs kfd/rls: dumps HWS runlists on all GPUs Signed-off-by:Yong Zhao <yong.zhao@amd.com> Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by:
Oded Gabbay <oded.gabbay@gmail.com> Signed-off-by:
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Felix Kuehling authored
This can be used by KFD for debugging features, such as dumping HQDs in debugfs. Signed-off-by:
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Felix Kuehling authored
This counts the queue offset in register index, not register address. Signed-off-by:
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Felix Kuehling authored
Don't count SDMA queues towards compute HQD oversubscription when deciding whether to create a chained runlist. Signed-off-by:
Jay Cornwall <Jay.Cornwall@amd.com> Signed-off-by:
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Felix Kuehling authored
Allow HWS to to execute multiple processes on the hardware concurrently. The number of concurrent processes is limited by the number of VMIDs allocated to the HWS. A module parameter can be used for limiting this further or turn it off altogether (mainly for debugging purposes). Signed-off-by:
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- 04 Dec, 2017 1 commit
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Kent Russell authored
Just print a pointer instead of casting v2: Remove the 0x prefix, since %p prints that automatically, and remove it from one other spot as well Signed-off-by:
Kent Russell <kent.russell@amd.com> Reviewed-by:
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- 27 Nov, 2017 2 commits
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Philip Yang authored
After debugger is registered, the pqm_destroy_queue fails because is_debug is true, the queue should not be removed from process_queue_list since the count is not reduced. Test application calls debugger unregister without register debugger, add null pointer check protection to avoid crash for this case Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Signed-off-by:
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Felix Kuehling authored
Use proper powerplay function. This fixes OpenCL initialization problems. Signed-off-by:
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- 24 Nov, 2017 1 commit
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Yong Zhao authored
Signed-off-by:
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- 14 Nov, 2017 4 commits
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Felix Kuehling authored
A second-level user mode trap handler can be installed. The CWSR trap handler jumps to the secondary trap handler conditionally for any conditions not handled by it. This can be used e.g. for debugging or catching math exceptions. When CWSR is disabled, the user mode trap handler is installed as first level trap handler. Signed-off-by:
Shaoyun.liu <shaoyun.liu@amd.com> Signed-off-by:
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Felix Kuehling authored
This hardware feature allows the GPU to preempt shader execution in the middle of a compute wave, save the state and restore it later to resume execution. Memory for saving the state is allocated per queue in user mode and the address and size passed to the create_queue ioctl. The size depends on the number of waves that can be in flight simultaneously on a given ASIC. Signed-off-by:
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Felix Kuehling authored
The trap handler is like an interrupt handler running on the GPU compute unit. It is needed for supporting CWSR (compute wave save/restore). This file defines an array with the pre-compiled GFXv8 shader ISA. The assembly code is included for reference in #if 0 ... #endif. Signed-off-by:
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Felix Kuehling authored
The PQM doesn't change after process creation. So initialize it in kfd_create_process_device_data. Signed-off-by:
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- 06 Nov, 2017 2 commits
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Felix Kuehling authored
Replace (ffs(size) - 1) with order_base_2(size) as a more straight forward way to get log2 of buffer sizes. Signed-off-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Felix Kuehling authored
Don't use sizeof(uint32_t) or similar types for hardware or firmware DWORD size. The hardware and firmware don't care about Linux types. Signed-off-by:
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- 01 Nov, 2017 5 commits
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Philip Cox authored
Signed-off-by:
Philip Cox <Philip.Cox@amd.com> Signed-off-by:
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Felix Kuehling authored
Signed-off-by:
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Philip Cox authored
Signed-off-by:
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Felix Kuehling authored
Save wptr in hqd_sdma_destroy, restore it in hqd_sdma_load. Also read updated wptr from user mode when resuming an SDMA queue. Signed-off-by:
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Felix Kuehling authored
Add wptr and mm parameters to hqd_sdma_load and pass these parameters from device_queue_manager through the mqd_manager. SDMA doesn't support polling while the engine believes it's idle. The driver must update the wptr. The new parameters will be used for looking up the updated value from the specified mm when SDMA queues are resumed after being disabled. Signed-off-by:
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- 21 Dec, 2017 4 commits
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git://people.freedesktop.org/~agd5f/linuxDave Airlie authored
* 'drm-next-4.16' of git://people.freedesktop.org/~agd5f/linux: (171 commits) drm/amdgpu: fix test for shadow page tables drm/amd/display: Expose dpp1_set_cursor_attributes drm/amd/display: Update FMT and OPPBUF functions drm/amd/display: check for null before calling is_blanked drm/amd/display: dal 3.1.27 drm/amd/display: Fix unused variable warnings. drm/amd/display: Only blank DCN when we have set_blank implementation drm/amd/display: Put dcn_mi_registers with other structs drm/amd/display: hubp refactor drm/amd/display: integrating optc pseudocode drm/amd/display: Call validate_fbc should_enable_fbc drm/amd/display: Clean up DCN cursor code drm/amd/display: fix 180 full screen pipe split drm/amd/display: reprogram surface config on scaling change drm/amd/display: Remove dwbc from pipe_ctx drm/amd/display: Use the maximum link setting which EDP reported. drm/amd/display: Add hdr_supported flag drm/amd/display: fix global sync param retrieval when not pipe splitting drm/amd/display: Update HUBP drm/amd/display: fix rotated surface scaling ...
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git://git.kernel.org/pub/scm/linux/kernel/git/tomba/linuxDave Airlie authored
omapdrm changes for v4.16 * support memory bandwidth limits * DSI command mode panel cleanups for N9 * DMM error handling * tag 'omapdrm-4.16' of git://git.kernel.org/pub/scm/linux/kernel/git/tomba/linux: (27 commits) drm: omapdrm: Simplify platform registration drm: omapdrm: Remove filename from header and fix copyright tag drm/omap: DMM: Check for DMM readiness after successful transaction commit drm/omap: DMM: Print information if we received an error interrupt drm/omap: DMM: In case of error/timeout in wait_status() print the reason drm/omap: DMM: Fix DMM_IRQSTAT_ERR_MASK definition drm: omapdrm: Deconstruct the omap_drv.h header. drm: omapdrm: venc: Return error code on OF parsing failure drm: omapdrm: dpi: Remove dpi_data port_initialized field drm: omapdrm: dss: Make dss_dump_clocks() function static drm: omapdrm: dss: Set the DMA coherent mask drm: omapdrm: Remove unused omap_dss_find_device() function drm: omapdrm: Pass drm_device to omap_gem_resume() drm: omapdrm: dpi: Don't treat GPIO probe deferral as an error drm/omap: panel-dsi-cm: switch to gpiod drm/omap: panel-dsi-cm: add external backlight support drm/omap: panel-dsi-cm: add physical size support drm/omap: panel-dsi-cm: add regulator support drm/omap: panel-dsi-cm: fix driver drm/omap: add support for physical size hints from display drivers ...
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https://github.com/jsarha/linuxDave Airlie authored
drm/tilcdc changes for 4.16 * tag 'tilcdc-4.16' of https://github.com/jsarha/linux: drm/tilcdc: make tilcdc_mode_hvtotal() static drm/tilcdc: Remove drm_framebuffer_get() and *_put() calls drm/tilcdc: ensure nonatomic iowrite64 is not used
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git://anongit.freedesktop.org/drm/drm-intelDave Airlie authored
- Fix documentation build issues (Randy, Markus) - Fix timestamp frequency calculation for perf on CNL (Lionel) - New DMC firmware for Skylake (Anusha) - GTT flush fixes and other GGTT write track and refactors (Chris) - Taint kernel when GPU reset fails (Chris) - Display workarounds organization (Lucas) - GuC and HuC initialization clean-up and fixes (Michal) - Other fixes around GuC submission (Michal) - Execlist clean-ups like caching ELSP reg offset and improving log readability (Chri\ s) - Many other improvements on our logs and dumps (Chris) - Restore GT performance in headless mode with DMC loaded (Tvrtko) - Stop updating legacy fb parameters since FBC is not using anymore (Daniel) - More selftest improvements (Chris) - Preemption fixes and improvements (Chris) - x86/early-quirks improvements for Intel graphics stolen memory. (Joonas, Matthew) - Other improvements on Stolen Memory code to be resource centric. (Matthew) - Improvements and fixes on fence allocation/release (Chris). GVT: - fixes for two coverity scan errors (Colin) - mmio switch code refine (Changbin) - more virtual display dmabuf fixes (Tina/Gustavo) - misc cleanups (Pei) - VFIO mdev display dmabuf interface and gvt support (Tina) - VFIO mdev opregion support/fixes (Tina/Xiong/Chris) - workload scheduling optimization (Changbin) - preemption fix and temporal workaround (Zhenyu) - and misc fixes after refactor (Chris) * tag 'drm-intel-next-2017-12-14' of git://anongit.freedesktop.org/drm/drm-intel: (87 commits) drm/i915: Update DRIVER_DATE to 20171214 drm/i915: properly init lockdep class drm/i915: Show engine state when hangcheck detects a stall drm/i915: make CS frequency read support missing more obvious drm/i915/guc: Extract doorbell verification into a function drm/i915/guc: Extract clients allocation to submission_init drm/i915/guc: Extract doorbell creation from client allocation drm/i915/guc: Call invalidate after changing the vfunc drm/i915/guc: Extract guc_init from guc_init_hw drm/i915/guc: Move GuC workqueue allocations outside of the mutex drm/i915/guc: Move shared data allocation away from submission path drm/i915: Unwind i915_gem_init() failure drm/i915: Ratelimit request allocation under oom drm/i915: Allow fence allocations to fail drm/i915: Mark up potential allocation paths within i915_sw_fence as might_sleep drm/i915: Don't check #active_requests from i915_gem_wait_for_idle() drm/i915/fence: Use rcu to defer freeing of irq_work drm/i915: Dump the engine state before declaring wedged from wait_for_engines() drm/i915: Bump timeout for wait_for_engines() drm/i915: Downgrade misleading "Memory usable" message ...
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- 20 Dec, 2017 16 commits
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Christian König authored
They don't work 100% correctly at the moment. Reviewed-and-Tested-by:
Michel Dänzer <michel.daenzer@amd.com> Signed-off-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Yue Hin Lau authored
Signed-off-by:
Yue Hin Lau <Yuehin.Lau@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Eric Bernstein authored
Updates to FMT and OPPBUF programming from HW team pseudocode review. Signed-off-by:
Eric Bernstein <eric.bernstein@amd.com> Reviewed-by:
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Yue Hin Lau authored
Signed-off-by:
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Andrew Jiang authored
Signed-off-by:
Andrew Jiang <Andrew.Jiang@amd.com> Reviewed-by:
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Leo (Sunpeng) Li authored
... since linux kernel compile treats warnings as errors. Signed-off-by:
Leo (Sunpeng) Li <sunpeng.li@amd.com> Reviewed-by:
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Yue Hin Lau authored
Also rename timing_generator to optc Signed-off-by:
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Eric Bernstein authored
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Yue Hin Lau authored
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Yue Hin Lau authored
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Harry Wentland authored
validate_fbc never fails a modeset. It's simply used to decide whether to use FBC or not. Calling it validate_fbc might be confusing to some so rename it to should_enable_fbc. With that let's also remove the DC_STATUS return code and return bool and make enable_fbc a void function since we never check it's return value and probably never want to anyways. Signed-off-by:
Roman Li <Roman.Li@amd.com> Acked-by:
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Eric Bernstein authored
Signed-off-by:
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Dmytro Laktyushkin authored
Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
Yongqiang Sun <yongqiang.sun@amd.com> Acked-by:
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Eric Yang authored
When plane size changes, we need to reprogram surface pitch in addition to viewport and scaler. This change is a conservative way to make this happen. However it could be more optimized to move pitch programming into mem_program_viewport. Signed-off-by:
Eric Yang <Eric.Yang2@amd.com> Reviewed-by:
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Eric Bernstein authored
Signed-off-by:
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Hugo Hu authored
Signed-off-by:
Hugo Hu <hugo.hu@amd.com> Reviewed-by:
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