1. 16 Apr, 2013 2 commits
    • Laurent Pinchart's avatar
      drm: Destroy property blobs at mode config cleanup time · 87d24fc3
      Laurent Pinchart authored
      Property blob objects need to be destroyed when cleaning up to avoid
      memory leaks. Go through the list of all blobs in the
      drm_mode_config_cleanup() function and destroy them.
      
      The drm_mode_config_cleanup() function needs to be moved after the
      drm_property_destroy_blob() declaration. Move drm_mode_config_init() as
      well to keep the functions together.
      Signed-off-by: default avatarLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
      Reviewed-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
      87d24fc3
    • Dave Airlie's avatar
      Merge tag 'drm-intel-next-2013-04-06' of... · 28184f22
      Dave Airlie authored
      Merge tag 'drm-intel-next-2013-04-06' of git://people.freedesktop.org/~danvet/drm-intel into drm-next
      
      Daniel writes:
      Since I expect Linus to open the merge window in about a week I guess this
      is the last i915 feature pull for 3.10. Highlights:
      Updated testing tree for -next. Highlights:
      - Corner case fixes discovered with static analyzers (Damien).
      - More fixes to combat unclaimed register errors on Haswell (Paulo).
      - Some small fixes to the gpu turbo code (Rodrigo+Ben), Ben has more
        fixes for overclocking support pending.
      - More prep work for fastboot from Chris.
      - VT-switchless suspend/resume from Jesse.
      - The prep work of Egbert Eich's hpd irq storm handling. Hopefully we can
        squeeze in the actual storm handling code for 3.10 ...
      - More convenience helpers for Imre's sg iterator. Core parts acked by
        Andrew Morton.
      - A bit of backlight code cleanup from Jani.
      - Fixed ilk gpu reset (Jesse).
      - Reduced color range handling fixes for VLV (Ville).
      
      The big item here is though the introduction of pipe_config to properly
      pre-compute the desired modeset state before touching the hw. Together
      with some very basic support to read out the current config from the hw
      and compare the state with the sw tracking. This is all prep work for more
      reliable fastboot, atomic modesets and other cool features. Stuff
      converted to the new world includes:
      - Most simple pipe attributes (reduce color range, pixel multiplier).
      - Pipe bpp/dither handling.
      - Some convenience flags like ->has_pch_encoder to simplify the code flow.
      - (Almost) DP clock handling, had to be reverted since part of a prep
        patch was lost in rebasing ...
      Expect a lot of patches for this throughout 3.11, there's tons of work
      till we have all state properly tracked for fastbooting to woExpect a lot
      of patches for this throughout 3.11, there's tons of work till we have all
      state properly tracked for fastbooting to work.
      
      For 3.10 I have a bunch of fixes queued up and I plan to send them all out
      at the end of this week. I need to shuffle patches in my -next queue a bit
      so that we don't but feature-y stuff in there, too. The main thing I'd
      like to sneak in is Egbert's hpd irq storm handling, which should be
      pretty low-risk since all the infrastructure work has landed already. I
      also have the oops fix pending, but that only mustered review before the
      w/e and giving how hairy that part of our modeset code is, I want to give
      it some more testing before forwarding.
      
      Note: annarchy.fd.o seems to run out of disk space, so couldn't push the
      usual for-airlied branch. Tag should work though.
      
      Note 2: I've had to do a backmerge since conflicts grew too ugly, but the
      upstream -rc I've backmerged is already in your drm-next.
      
      * tag 'drm-intel-next-2013-04-06' of git://people.freedesktop.org/~danvet/drm-intel: (75 commits)
        drm/i915: info level for simulated gpu hang dmesg notice
        drm/i915: revert eDP bpp clamping code changes
        Revert "drm/i915: fix DP get_hw_state return value"
        drm/i915: Don't use the HDMI port color range bit on Valleyview
        drm/i915: Set PIPECONF color range bit on Valleyview
        drm/i915: extract i9xx_set_pipeconf
        drm/i915: Add no-lvds quirk for Fujitsu Esprimo Q900
        drm/i915: create pipe_config->dpll for clock state
        drm/i915: hw readout support for ->has_pch_encoders
        drm/i915: add hw state readout/checking for pipe_config
        drm/i915: rip out superflous is_dp&is_cpu_edp tracking
        drm/i915: remove leaky eDP functions
        drm/i915: track dp target_clock in pipe_config
        drm/i915: move dp_m_n computation to dp_encoder->compute_config
        drm/i915: clear up the fdi/dp set_m_n confusion
        drm/i915: Fix sdvo connector get_hw_state function
        drm/i915: drop DPFLIPSTAT enables on VLV v3
        drm/i915: add Punit read/write routines for VLV v2
        drm/i915: panel power sequencing for VLV eDP v2
        drm/i915/dp: fix up VLV DP handling v2
        ...
      28184f22
  2. 12 Apr, 2013 8 commits
  3. 06 Apr, 2013 1 commit
  4. 05 Apr, 2013 7 commits
    • Daniel Vetter's avatar
      drm/i915: revert eDP bpp clamping code changes · 57c21963
      Daniel Vetter authored
      The behaviour around handling the eDP bpp value from vbt has been
      slightly changed in
      
      commit 36008365
      Author: Daniel Vetter <daniel.vetter@ffwll.ch>
      Date:   Wed Mar 27 00:44:59 2013 +0100
      
          drm/i915: convert DP autodither code to new infrastructure
      
      The old behaviour was that we used the plane's bpp (usually 24bpp) for
      computing the dp link bw, but set up the pipe with the bpp value from
      vbt if available. This takes the vbt bpp override into account even
      for the dp link bw configuration.
      
      On Paulo's hsw machine this resulted in a slower link clock and a
      black screen - but the mode actually /should/ fit even with the lower
      clock. Until we've cleared up simply stay bug-for-bug compatible with
      the old code.
      
      While at it, also restore a debug message lost in:
      
      commit 4e53c2e0
      Author: Daniel Vetter <daniel.vetter@ffwll.ch>
      Date:   Wed Mar 27 00:44:58 2013 +0100
      
          drm/i915: precompute pipe bpp before touching the hw
      
      Cc: Paulo Zanoni <przanoni@gmail.com>
      Reviewed-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
      Tested-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      57c21963
    • Daniel Vetter's avatar
      Revert "drm/i915: fix DP get_hw_state return value" · 2af8898b
      Daniel Vetter authored
      This reverts commit deb18211.
      
      It completely breaks the logic, since when we fall through to the end
      of the function we actually _have_ figured out the correct pipe.
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      2af8898b
    • Ville Syrjälä's avatar
      drm/i915: Don't use the HDMI port color range bit on Valleyview · 83a2af88
      Ville Syrjälä authored
      VLV docs still list the the color range selection bit for the HDMI
      ports, but for DP ports it has been repurposed.
      
      I have no idea whether the HDMI color range selection bit still works
      on VLV, but since we now have to use the PIPECONF color range bit for
      DP, we might as well do the same for HDMI.
      Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
      Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      83a2af88
    • Ville Syrjälä's avatar
      drm/i915: Set PIPECONF color range bit on Valleyview · 9c8e09b7
      Ville Syrjälä authored
      VLV has the color range selection bit in the PIPECONF register.
      Configure it appropriately.
      Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
      Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
      [danvet: fixup rebase issues due to slightly different baseline.]
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      9c8e09b7
    • Daniel Vetter's avatar
      drm/i915: extract i9xx_set_pipeconf · 84b046f3
      Daniel Vetter authored
      Prep-patch to improve the bpc handling in a next patch.
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      84b046f3
    • Christian Lamparter's avatar
      drm/i915: Add no-lvds quirk for Fujitsu Esprimo Q900 · 9e9dd0e8
      Christian Lamparter authored
      The "Mobile Sandy Bridge CPUs" in the Fujitsu Esprimo Q900
      mini desktop PCs are probably misleading the LVDS detection
      code in intel_lvds_supported. Nothing is connected to the
      LVDS ports in these systems.
      Signed-off-by: default avatarChristian Lamparter <chunkeey@googlemail.com>
      Cc: stable@vger.kernel.org
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      9e9dd0e8
    • Dave Airlie's avatar
      Merge tag 'drm-intel-next-2013-03-23' of... · 399403c7
      Dave Airlie authored
      Merge tag 'drm-intel-next-2013-03-23' of git://people.freedesktop.org/~danvet/drm-intel into drm-next
      
      Daniel writes:
      Highlights:
      - Imre's for_each_sg_pages rework (now also with the stolen mem backed
        case fixed with a hack) plus the drm prime sg list coalescing patch from
        Rahul Sharma. I have some follow-up cleanups pending, already acked by
        Andrew Morton.
      - Some prep-work for the crazy no-pch/display-less platform by Ben.
      - Some vlv patches, by far not all (Jesse et al).
      - Clean up the HDMI/SDVO #define confusion (Paulo)
      - gen2-4 vblank fixes from Ville.
      - Unclaimed register warning fixes for hsw (Paulo). More still to come ...
      - Complete pageflips which have been stuck in a gpu hang, should prevent
        stuck gl compositors (Ville).
      - pm patches for vt-switchless resume (Jesse). Note that the i915 enabling
        is not (yet) included, that took a bit longer to settle. PM patches are
        acked by Rafael Wysocki.
      - Minor fixlets all over from various people.
      
      * tag 'drm-intel-next-2013-03-23' of git://people.freedesktop.org/~danvet/drm-intel: (79 commits)
        drm/i915: Implement WaSwitchSolVfFArbitrationPriority
        drm/i915: Set the VIC in AVI infoframe for SDVO
        drm/i915: Kill a strange comment about DPMS functions
        drm/i915: Correct sandybrige overclocking
        drm/i915: Introduce GEN7_FEATURES for device info
        drm/i915: Move num_pipes to intel info
        drm/i915: fixup pd vs pt confusion in gen6 ppgtt code
        style nit: Align function parameter continuation properly.
        drm/i915: VLV doesn't have HDMI on port C
        drm/i915: DSPFW and BLC regs are in the display offset range
        drm/i915: set conservative clock gating values on VLV v2
        drm/i915: fix WaDisablePSDDualDispatchEnable on VLV v2
        drm/i915: add more VLV IDs
        drm/i915: use VLV DIP routines on VLV v2
        drm/i915: add media well to VLV force wake routines v2
        drm/i915: don't use plane pipe select on VLV
        drm: modify pages_to_sg prime helper to create optimized SG table
        drm/i915: use for_each_sg_page for setting up the gtt ptes
        drm/i915: create compact dma scatter lists for gem objects
        drm/i915: handle walking compact dma scatter lists
        ...
      399403c7
  5. 04 Apr, 2013 5 commits
  6. 03 Apr, 2013 17 commits