- 10 May, 2016 2 commits
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Arnd Bergmann authored
Merge tag 'samsung-dt-devfreq-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/late Merge "ARM: dts: exynos: Devfreq for v4.7: from Krzysztof Kozłowski: Topic branch for Device Tree changes adding new generic devfreq driver, for v4.7: 1. Add bus nodes for Exynos3250, Exynos4x12, Exynos4210 and Exynos542x. 2. Split out common PPMU (Performance Monitoring Unit) nodes into separate DTSI. The PPMU provides performance data for devfreq. 3. Add NoCP (Network on Chip Probe) node for Exynos542x. On this SoC, like PPMU on older designs, provides performance data for devfreq. 4. Enable DFVS (Dynamic Voltage and Frequency Scaling) on boards: - Exynos3250 Rinato, - Exynos4412 Odroid-X/X2/U3 and Trats2, - Exynos5422 Odroid XU3/XU3-Lite/XU4. * tag 'samsung-dt-devfreq-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: ARM: dts: exynos: Add support of Bus frequency using VDD_INT for exynos5422-odroidxu3 ARM: dts: exynos: Add bus nodes using VDD_INT for Exynos542x SoC ARM: dts: exynos: Add NoC Probe dt node for Exynos542x SoC ARM: dts: exynos: Add support of bus frequency for exynos4412-trats/odroidu3 ARM: dts: exynos: Expand the voltage range of buck1/3 regulator for exynos4412-odroidu3 ARM: dts: exynos: Add support of bus frequency using VDD_INT for exynos3250-rinato ARM: dts: exynos: Add exynos4412-ppmu-common dtsi to delete duplicate PPMU nodes ARM: dts: exynos: Add bus nodes using VDD_MIF for Exynos4210 ARM: dts: exynos: Add bus nodes using VDD_INT for Exynos4x12 ARM: dts: exynos: Add bus nodes using VDD_MIF for Exynos4x12 ARM: dts: exynos: Add bus nodes using VDD_INT for Exynos3250 ARM: dts: exynos: Add DMC bus frequency for exynos3250-rinato/monk ARM: dts: exynos: Add DMC bus node for Exynos3250 clk: samsung: exynos542x: Add the clock id for ACLK dt-bindings: clock: Add the clock id for ACLK clock of Exynos542x SoC
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Arnd Bergmann authored
Merge tag 'imx-dt-clkdep-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/late Merge "The i.MX device tree updates with new clocks for 4.7" from Shawn Guo: - Add LCDIF and FlexCAN device support for i.MX7D - New support i.MX7D based Nitrogen7 board from Boundary Devices - Add display support for vf610-colibri board * tag 'imx-dt-clkdep-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: ARM: dts: vf610-colibri: enable display controller ARM: dts: vf610: add display nodes ARM: dts: imx: add Boundary Devices Nitrogen7 board ARM: dts: imx7d: add flexcan support ARM: dts: imx7d: add lcdif support clk: imx: vf610: fix whitespace in vf610-clock.h clk: imx: vf610: add TCON ipg clock clk: imx: vf610: fix DCU clock tree clk: imx: add ckil clock for i.MX7 clk: imx: vf610: add suspend/resume support clk: imx: vf610: add WKPU unit clk: imx: vf610: leave DDR clock on clk: imx: clk-gate2: allow custom gate configuration clk: imx6sx: Register SAI clocks as shared clocks
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- 09 May, 2016 3 commits
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Arnd Bergmann authored
Merge tag 'tegra-for-4.7-xusb-no-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/late Merge "ARM: tegra: Enable the XUSB controller" from Thierry Reding: These changes add support for the XUSB controller on Tegra124. It is an XHCI compatible controller that replaces the existing EHCI controllers. Support is enabled on Venice2, Jetson TK1 and Nyan-based Chromebooks. * tag 'tegra-for-4.7-xusb-no-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: ARM: tegra: Enable XUSB on Nyan ARM: tegra: Enable XUSB on Jetson TK1 ARM: tegra: Enable XUSB on Venice2 ARM: tegra: Add Tegra124 XUSB controller ARM: tegra: Move Tegra124 to the new XUSB pad controller binding
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Arnd Bergmann authored
This is a prerequisite for enabling the Tegra XUSB, all the branches should be merged already at the time we get here. * tegra/pci: PCI: tegra: Support per-lane PHYs dt-bindings: pci: tegra: Update for per-lane PHYs phy: tegra: Add Tegra210 support phy: Add Tegra XUSB pad controller support dt-bindings: phy: tegra-xusb-padctl: Add Tegra210 support dt-bindings: phy: Add NVIDIA Tegra XUSB pad controller binding phy: core: Allow children node to be overridden clk: tegra: Add interface to enable hardware control of SATA/XUSB PLLs * tegra/usb: usb: xhci: tegra: Add Tegra210 support usb: xhci: Add NVIDIA Tegra XUSB controller driver dt-bindings: usb: xhci-tegra: Add Tegra210 XUSB controller support dt-bindings: usb: Add NVIDIA Tegra XUSB controller binding phy: tegra: Add Tegra210 support phy: Add Tegra XUSB pad controller support dt-bindings: phy: tegra-xusb-padctl: Add Tegra210 support dt-bindings: phy: Add NVIDIA Tegra XUSB pad controller binding phy: core: Allow children node to be overridden clk: tegra: Add interface to enable hardware control of SATA/XUSB PLLs
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Arnd Bergmann authored
Merge tag 'renesas-arm64-dt-pm-domain-for-v4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/late Merge "Renesas ARM64 Based SoC DT PM Domain Updates for v4.7" from Simon Horman: * Add SYSC PM Domains to DT of r8a7795 SoC * tag 'renesas-arm64-dt-pm-domain-for-v4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: arm64: dts: r8a7795: Use SYSC "always-on" PM Domain arm64: dts: r8a7795: Add SYSC PM Domains arm64: dts: r8a7795: Don't disable referenced optional clocks arm64: dts: salvator-x: populate EXTALR arm64: dts: r8a7795: enable PCIe on Salvator-X arm64: dts: r8a7795: Add PCIe nodes arm64: dts: r8a7795: Use USB3.0 fallback compatibility string arm64: dts: r8a7795: Add CAN support arm64: dts: r8a7795: Add CAN external clock support
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- 03 May, 2016 14 commits
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Chanwoo Choi authored
This patch adds the bus device tree nodes for INT (Internal) block to enable the AMBA bus frequency scaling and add the NoC (Network on Chip) Probe Device Tree node to measure the bandwidth for AMBA AXI bus. The WCORE bus bus is parent device in INT block using VDD_INT. Signed-off-by:
Chanwoo Choi <cw00.choi@samsung.com> Tested-by:
Markus Reichl <m.reichl@fivetechno.de> Tested-by:
Anand Moon <linux.amoon@gmail.com> Reviewed-by:
Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by:
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Chanwoo Choi authored
This patch adds the AMBA bus nodes using VDD_INT for Exynos542x SoC. Exynos542x has the following AMBA buses to translate data between DRAM and sub-blocks. Following list specifies the detailed correlation between sub-block and clock: - CLK_DOUT_ACLK400_WCORE clock for WCORE's AXI - CLK_DOUT_ACLK100_NOC for NoC (Network on Chip)'s AXI - CLK_DOUT_PCLK200_FSYS for FSYS's APB - CLK_DOUT_ACLK200_FSYS for FSYS's AXI - CLK_DOUT_ACLK200_FSYS2 for FSYS2's AXI - CLK_DOUT_ACLK333 for MFC's AXI - CLK_DOUT_ACLK266 for GEN's AXI - CLK_DOUT_ACLK66 for PERIC/PERIR's AXI - CLK_DOUT_ACLK333_G2D for G2D's AXI - CLK_DOUT_ACLK266_G2D for ACP's AXI - CLK_DOUT_ACLK300_JPEG for JPEG's AXI - CLK_DOUT_ACLK166 for JPEG's APB - CLK_DOUT_ACLK300_DISP1 for FIMD's AXI - CLK_DOUT_ACLK400_DISP1 for DISP1's AXI - CLK_DOUT_ACLK300_GSCL for GSCL Scaler's AXI - CLK_DOUT_ACLK400_MSCL for MSCL's AXI Signed-off-by:
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Chanwoo Choi authored
This patch adds the NoCP (Network on Chip Probe) Device Tree node to measure the bandwidth of memory and g3d in Exynos542x SoC. Signed-off-by:
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Chanwoo Choi authored
This patch adds the bus device tree nodes for both MIF (Memory) and INT (Internal) block to enable the bus frequency. The DMC bus is parent device in MIF block using VDD_MIF and the LEFTBUS bus is parent device in INT block using VDD_INT. Signed-off-by:
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Chanwoo Choi authored
This patch expands the voltage range of buck1/3 regulator due to as following: - MIF (Memory Interface) bus frequency needs the range of '900 - 1100 mV'. - INT (Internal) bus frequency needs the range of '900 - 1050 mV'. Signed-off-by:
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Chanwoo Choi authored
This patch adds the bus device-tree nodes of INT (internal) block to enable the bus frequency scaling. The following sub-blocks share the VDD_INT power source: - LEFTBUS (parent device) - RIGHTBUS - PERIL - LCD0 - FSYS - MCUISP / ISP - MFC The LEFTBUS is parent device with devfreq ondemand governor and the rest of devices depend on the LEFTBUS device. Signed-off-by:
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Chanwoo Choi authored
This patch adds the exynos4412-ppmu-common.dtsi to remove duplicate PPMU nodes because exynos3250-rinato/monk, exynos4412-trats2/odroidu3 has the same PPMU device tree node. Signed-off-by:
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Chanwoo Choi authored
This patch adds the bus nodes for Exynos4210 SoC. Exynos4210 SoC has one power line for all buses to translate data between DRAM and sub-blocks. Following list specifies the detailed relation between DRAM and sub-blocks: - DMC/ACP clock for DMC (Dynamic Memory Controller) - ACLK200 clock for LCD0 - ACLK100 clock for PERIL/PERIR/MFC(PCLK) - ACLK160 clock for CAM/TV/LCD0/LCD1 - ACLK133 clock for FSYS/GPS - GDL/GDR clock for LEFTBUS/RIGHTBUS - SCLK_MFC clock for MFC Signed-off-by:
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Chanwoo Choi authored
This patch adds the bus nodes using VDD_INT for Exynos4x12 SoC. Exynos4x12 has the following AXI buses to translate data between DRAM and sub-blocks. Following list specifies the detailed relation between DRAM and sub-blocks: - ACLK100 clock for PERIL/PERIR/MFC(PCLK) - ACLK160 clock for CAM/TV/LCD : The minimum clock of ACLK160 should be over 160MHz. When drop the clock under 160MHz, show the broken image. - ACLK133 clock for FSYS - GDL clock for LEFTBUS - GDR clock for RIGHTBUS - SCLK_MFC clock for MFC Signed-off-by:
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Chanwoo Choi authored
This patch adds the bus nodes using VDD_MIF for Exynos4x12 SoC. Exynos4x12 has the following AXI buses to translate data between DRAM and DMC/ACP/C2C. Signed-off-by:
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Chanwoo Choi authored
This patch adds the bus nodes using VDD_INT for Exynos3250 SoC. Exynos3250 has following AXI buses to translate data between DRAM and sub-blocks. Following list specifies the detailed relation between DRAM and sub-blocks: - ACLK400 clock for MCUISP - ACLK266 clock for ISP - ACLK200 clock for FSYS - ACLK160 clock for LCD0 - ACLK100 clock for PERIL - GDL clock for LEFTBUS - GDR clock for RIGHTBUS - SCLK_MFC clock for MFC Signed-off-by:
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Chanwoo Choi authored
This patch adds the DMC (Dynamic Memory Controller) bus frequency node which includes the devfreq-events and regulator properties. The bus frequency support the DVFS (Dynamic Voltage Frequency Scaling) feature with ondemand governor. The devfreq-events (ppmu_dmc0*) can monitor the utilization of DMC bus on runtime and the buck1_reg (VDD_MIF power line) supplies the power to the DMC block. Signed-off-by:
MyungJoo Ham <myungjoo.ham@samsung.com> Signed-off-by:
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Chanwoo Choi authored
This patch adds the DMC (Dynamic Memory Controller) bus node for Exynos3250 SoC. The DMC is an AMBA AXI-compliant slave to interface external JEDEC standard SDRAM devices. The bus includes the OPP tables and the source clock for DMC block. Following list specifies the detailed relation between the clock and DMC block: - The source clock of DMC block : div_dmc Signed-off-by:
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git://linuxtv.org/snawrocki/samsungKrzysztof Kozlowski authored
Merge tag 'clk-v4.7-exynos542x' of git://linuxtv.org/snawrocki/samsung into for-v4.7-late/dts-exynos-devfreq Addition of IDs for Exynos542x SoC AMBA AXI bus clocks. These IDs are needed before we start using them in DTS.
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- 29 Apr, 2016 21 commits
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Thierry Reding authored
Add XUSB pad controller and XUSB controller device tree nodes and enable them with a configuration for the Nyan boards. Signed-off-by:Thierry Reding <treding@nvidia.com>
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Thierry Reding authored
Add XUSB pad controller and XUSB controller device tree nodes and enable them with a configuration for the Jetson TK1 board. Signed-off-by: -
Thierry Reding authored
Add XUSB pad controller and XUSB controller device tree nodes and enable them with a configuration for the Venice2 board. Signed-off-by: -
Thierry Reding authored
Add a device tree node for the Tegra XUSB controller. It contains a phandle to the XUSB pad controller for control of the PHYs assigned to the USB ports. Signed-off-by: -
Thierry Reding authored
Use the new XUSB pad controller binding on Tegra124. Signed-off-by: -
Thierry Reding authored
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Thierry Reding authored
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Thierry Reding authored
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Thierry Reding authored
Parameterize more parts of the driver and add support for Tegra210. Acked-by:
Mathias Nyman <mathias.nyman@linux.intel.com> Signed-off-by:
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Thierry Reding authored
Add support for the on-chip XUSB controller present on Tegra SoCs. This controller, when loaded with external firmware, exposes an interface compliant with xHCI. This driver loads the firmware, starts the controller, and is able to service host-specific messages sent by the controller's firmware. The controller also supports USB device mode as well as powergating of the SuperSpeed and host-controller logic when not in use, but support for these is not yet implemented. Based on work by: Ajay Gupta <ajayg@nvidia.com> Bharath Yadav <byadav@nvidia.com> Andrew Bresticker <abrestic@chromium.org> Cc: Mathias Nyman <mathias.nyman@intel.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Acked-by:
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Thierry Reding authored
Extend the Tegra XUSB controller device tree binding with Tegra210 support. Acked-by:
Rob Herring <robh@kernel.org> Acked-by:
Stephen Warren <swarren@nvidia.com> Signed-off-by:
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Thierry Reding authored
Add device-tree binding documentation for the XUSB controller present on Tegra124 and later SoCs. This controller supports USB 3.0 via an xHCI compliant interface. Based on work by Andrew Bresticker <abrestic@chromium.org>. Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: Mathias Nyman <mathias.nyman@intel.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Acked-by:
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Thierry Reding authored
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Thierry Reding authored
The current XUSB pad controller bindings are insufficient to describe PHY devices attached to USB controllers. New bindings have been created to overcome these restrictions. As a side-effect each root port now is assigned a set of PHY devices, one for each lane associated with the root port. This has the benefit of allowing fine-grained control of the power management for each lane. Acked-by:
Bjorn Helgaas <bhelgaas@google.com> Signed-off-by:
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Thierry Reding authored
The XUSB pad controller allows PCIe lanes to be controlled individually, providing fine-grained control over their power state. Previous attempts at describing the XUSB pad controller in DT had erroneously assumed that all PCIe lanes were driven by the same PHY, and hence the PCI host controller would reference only a single PHY. Moving to a representation of per-lane PHYs requires that the operating system driver for the PCI host controller have access to the set of PHY devices that make up the connection of each root port in order to power up and down all of the lanes as necessary. Acked-by:
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Thierry Reding authored
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Thierry Reding authored
Add support for the XUSB pad controller found on Tegra210 SoCs. The hardware is roughly the same, but some of the registers have been moved around and the number and type of supported pads has changed. Signed-off-by: -
Thierry Reding authored
Add a new driver for the XUSB pad controller found on NVIDIA Tegra SoCs. This hardware block used to be exposed as a pin controller, but it turns out that this isn't a good fit. The new driver and DT binding much more accurately describe the hardware and are more flexible in supporting new SoC generations. Acked-by:
Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by:
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Thierry Reding authored
Extend the binding to cover the set of feature found in Tegra210. Acked-by:
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Thierry Reding authored
The NVIDIA Tegra XUSB pad controller provides a set of pads, each with a set of lanes that are used for PCIe, SATA and USB. A binding exists for the XUSB pad controller already, but it turned out not to be flexible enough to describe all aspects of the controller. In particular, the addition of XUSB support (for SuperSpeed USB) has shown that the existing binding is no longer suitable. Mark the old binding as deprecated and link to the new binding. Acked-by:
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Thierry Reding authored
In order to more flexibly support device tree bindings, allow drivers to override the container of the child nodes. By default the device node of the PHY provider is assumed to be the parent for children, but bindings may decide to add additional levels for better organization. Acked-by:
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