1. 13 Nov, 2017 10 commits
  2. 06 Nov, 2017 3 commits
  3. 02 Nov, 2017 2 commits
    • Richard Weinberger's avatar
      Merge tag 'nand/for-4.15' of git://git.infradead.org/l2-mtd · 16271224
      Richard Weinberger authored
      From Boris:
      "
      Core changes:
      * Add a flag to mark NANDs that require 3 address cycles to encode a
        page address
      * Set a default ECC/free layout when NAND_ECC_NONE is requested
      * Fix a bug in panic_nand_write()
      
      Driver changes:
      * Another batch of cleanups for the denali driver
      * Fix PM support in the atmel driver
      * Remove support for platform data in the omap driver
      * Fix subpage write in the omap driver
      * Fix irq handling in the mtk driver
      * Change link order of mtk_ecc and mtk_nand drivers to speed up boot
        time
      * Change log level of ECC error messages in the mxc driver
      * Patch the pxa3xx driver to support Armada 8k platforms
      * Add BAM DMA support to the qcom driver
      * Convert gpio-nand to the GPIO desc API
      * Fix ECC handling in the mt29f driver
      "
      16271224
    • Richard Weinberger's avatar
      Merge tag 'spi-nor/for-4.15' of git://git.infradead.org/l2-mtd · 20b2fc79
      Richard Weinberger authored
      This pull-request contains the following notable changes:
      
      From Cyrille:
      "
      Core changes:
      * Introduce system power management support.
      * New mechanism to select the proper .quad_enable() hook by JEDEC ID,
        when needed, instead of only by manufacturer ID.
      * Add support to new memory parts from Gigadevice, Winbond, Macronix and
        Everspin.
      
      Driver changes:
      * Maintainance for Cadence, Intel, Mediatek and STM32 drivers.
      "
      20b2fc79
  4. 31 Oct, 2017 1 commit
  5. 30 Oct, 2017 2 commits
    • Kuppuswamy Sathyanarayanan's avatar
      mtd: intel-spi: Add Intel Lewisburg PCH SPI super SKU PCI ID · ec0a9f62
      Kuppuswamy Sathyanarayanan authored
      This patch adds Intel Lewisburg PCH SPI serial flash controller super
      SKU PCI ID.
      Signed-off-by: default avatarKuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
      Acked-by: default avatarMika Westerberg <mika.westerberg@linux.intel.com>
      Signed-off-by: default avatarCyrille Pitchen <cyrille.pitchen@wedev4u.fr>
      ec0a9f62
    • Xiaolei Li's avatar
      mtd: nand: mtk: fix infinite ECC decode IRQ issue · 1d2fcdcf
      Xiaolei Li authored
      For MT2701 NAND Controller, there may generate infinite ECC decode IRQ
      during long time burn test on some platforms. Once this issue occurred,
      the ECC decode IRQ status cannot be cleared in the IRQ handler function,
      and threads cannot be scheduled.
      
      ECC HW generates decode IRQ each sector, so there will have more than one
      decode IRQ if read one page of large page NAND.
      
      Currently, ECC IRQ handle flow is that we will check whether it is decode
      IRQ at first by reading the register ECC_DECIRQ_STA. This is a read-clear
      type register. If this IRQ is decode IRQ, then the ECC IRQ signal will be
      cleared at the same time.
      Secondly, we will check whether all sectors are decoded by reading the
      register ECC_DECDONE. This is because the current IRQ may be not dealed
      in time, and the next sectors have been decoded before reading the
      register ECC_DECIRQ_STA. Then, the next sectors's decode IRQs will not
      be generated.
      Thirdly, if all sectors are decoded by comparing with ecc->sectors, then we
      will complete ecc->done, set ecc->sectors as 0, and disable ECC IRQ by
      programming the register ECC_IRQ_REG(op) as 0. Otherwise, wait for the
      next ECC IRQ.
      
      But, there is a timing issue between step one and two. When we read the
      reigster ECC_DECIRQ_STA, all sectors are decoded except the last sector,
      and the ECC IRQ signal is cleared. But the last sector is decoded before
      reading ECC_DECDONE, so the ECC IRQ signal is enabled again by ECC HW, and
      it means we will receive one extra ECC IRQ later. In step three, we will
      find that all sectors were decoded, then disable ECC IRQ and return.
      When deal with the extra ECC IRQ, the ECC IRQ status cannot be cleared
      anymore. That is because the register ECC_DECIRQ_STA can only be cleared
      when the register ECC_IRQ_REG(op) is enabled. But actually we have
      disabled ECC IRQ in the previous ECC IRQ handle. So, there will
      keep receiving ECC decode IRQ.
      
      Now, we read the register ECC_DECIRQ_STA once again before completing the
      ecc done event. This ensures that there will be no extra ECC decode IRQ.
      
      Also, remove writel(0, ecc->regs + ECC_IRQ_REG(op)) from irq handler,
      because ECC IRQ is disabled in mtk_ecc_disable(). And clear ECC_DECIRQ_STA
      in mtk_ecc_disable() in case there is a timeout to wait decode IRQ.
      
      Fixes: 1d6b1e46 ("mtd: mediatek: driver for MTK Smart Device")
      Cc: <stable@vger.kernel.org>
      Signed-off-by: default avatarXiaolei Li <xiaolei.li@mediatek.com>
      Signed-off-by: default avatarBoris Brezillon <boris.brezillon@free-electrons.com>
      1d2fcdcf
  6. 29 Oct, 2017 22 commits