- 06 Dec, 2017 22 commits
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Yue Hin Lau authored
Signed-off-by:
Yue Hin Lau <Yuehin.Lau@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Eric Bernstein authored
Also move some register definitions to common DCN regs. Signed-off-by:
Eric Bernstein <eric.bernstein@amd.com> Reviewed-by:
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Tony Cheng authored
Signed-off-by:
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Yue Hin Lau authored
no logic change Signed-off-by:
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Charlene Liu authored
Signed-off-by:
Charlene Liu <charlene.liu@amd.com> Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Yue Hin Lau authored
following the naming convention with correct prefix Signed-off-by:
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Yue Hin Lau authored
dcn version of update_dchub now uses hubbub instead of hwseq Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
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Colin Ian King authored
Variable pf2vf_ver is assigned but never read, it is redundant and hence can be removed. Cleans up clang warning: drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c:310:3: warning: Value stored to 'pf2vf_ver' is never read Reivewed-by:
Horace Chen <horace.chen@amd.com> Signed-off-by:
Colin Ian King <colin.king@canonical.com> Signed-off-by:
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Piotr Redlewski authored
When UVD bo is created, its size is based on the information from firmware header (ucode_size_bytes). The same value should be be used when programming UVD mc controller offsets, otherwise it can happen that (mmUVD_VCPU_CACHE_OFFSET2 + mmUVD_VCPU_CACHE_SIZE2) will point AMDGPU_GPU_PAGE_SIZE bytes after the UVD bo end. Second issue is that when programming the mmUVD_VCPU_CACHE_SIZE0 register, AMDGPU_UVD_FIRMWARE_OFFSET should be taken into account. If it isn't, (mmUVD_VCPU_CACHE_OFFSET2 + mmUVD_VCPU_CACHE_SIZE2) will always point AMDGPU_UVD_FIRMWARE_OFFSET bytes after the UVD bo end. v2: move firmware size calculation into macro definition v3: align firmware size to the gpu page size Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Piotr Redlewski <predlewski@gmail.com> Signed-off-by:
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Mikita Lipski authored
This feature synchronizes multiple displays with various timings to a display with the highest refresh rate it is enabled if edid caps flag multi_display_sync is set to one There are limitations on refresh rates allowed that can be synchronized. That would prevent from underflow and other potential corruptions. Multi display synchronization is using the same functions as timing_sync in order to minimize redunduncy and decision to disable synchronization is based on trigger parametre set in DM Feature is developed for DCN1 and DCE11 Signed-off-by:
Mikita Lipski <mikita.lipski@amd.com> Reviewed-by:
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Andrey Grodzovsky authored
Validates BO size against each requested domain's total memory. v2: Make GTT size check a MUST to allow fall back to GTT. Rmove redundant NULL check. Signed-off-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by:
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Christian König authored
It's pointless to have the same value twice, just always use max_pfn. Signed-off-by:
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Christian König authored
Not sure what that should originally been good for, but it doesn't seem to make any sense any more. Signed-off-by:
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Chunming Zhou authored
Otherwise, they could be optimized by scheduled fence. Signed-off-by:
Chunming Zhou <david1.zhou@amd.com> Reviewed-by:
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Xiangliang.Yu authored
Do ring clear before ring test, otherwise compute ring test will fail after gpu resetting. Still can't find the root cause, just workaround it. Signed-off-by:
Xiangliang.Yu <Xiangliang.Yu@amd.com> Acked-by:
Monk Liu <Monk.Liu@amd.com> Signed-off-by:
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Christian König authored
Just another alias for ttm_bo_unreserve. Signed-off-by:
Michel Dänzer <michel.daenzer@amd.com> Signed-off-by:
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Christian König authored
Consistently use the reservation object wrappers instead of accessing the ww_mutex directly. Additional to that use the reservation object wrappers directly instead of calling __ttm_bo_reserve with fixed parameters. v2: fix typo Signed-off-by:
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Christian König authored
Instead of having a confusing wrapper or call the underlying ww_mutex function directly. Signed-off-by:
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Christian König authored
Needed for the next patch and makes the code quite a bit easier to understand. Signed-off-by:
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Chunming Zhou authored
Signed-off-by:
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Chunming Zhou authored
We must remove the fence callback. Signed-off-by:
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Pixel Ding authored
Retry at drm_dev_register instead of amdgpu_device_init. Reviewed-by:
Pixel Ding <Pixel.Ding@amd.com> Signed-off-by:
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- 04 Dec, 2017 18 commits
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Harry Wentland authored
We no longer set the framebuffer address here so this is now dead code. Signed-off-by:
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Monk Liu authored
if app close CTX right after IB submit, gpu recover will fail to find out the entity behind this guilty job thus lead to no job skipping for this guilty job. to fix this corner case just move the increasement of job->karma out of the entity iteration. v2: only do karma increasment if bad->s_priority != KERNEL because we always consider KERNEL job be correct and always want to recover an unfinished kernel job (sometimes kernel job is interrupted by VF FLR or other GPU hang event) Signed-off-by:
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Monk Liu authored
Signed-off-by:
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pding authored
It introduces 900ms latency in exclusive mode which causes failure of driver loading. Host can resize the BAR before guest staring, so the resizing is not necessary here. Signed-off-by:
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pding authored
Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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pding authored
Also finalize kfd inside amdgpu_device_fini. kfd device_init needs SRIOV exclusive accessing. Try to gather exclusive accessing to reduce time consuming. Signed-off-by:
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Christian König authored
Just allocate the GART space and fill it. This prevents forcing the BO to be idle. v2: don't unbind/bind at all, just fill the allocated GART space Signed-off-by:
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Christian König authored
We actually don't bind here, but rather allocate GART space if necessary. Signed-off-by:
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Hawking Zhang authored
Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Acked-by:
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Christian König authored
Try to resize BAR0 to let CPU access all of VRAM. v2: rebased, style cleanups, disable mem decode before resize, handle gmc_v9 as well, round size up to power of two. v3: handle gmc_v6 as well, release and reassign all BARs in the driver. v4: rename new function to amdgpu_device_resize_fb_bar, reenable mem decoding only if all resources are assigned. v5: reorder resource release, return -ENODEV instead of BUG_ON(). v6: squash in rebase fix Signed-off-by: -
Horace Chen authored
The previous solution will create a zero buffer on the system domain and then move the zeroes to the VRAM. This will break the original data on the VRAM. Refine the code to create bo on VRAM domain directly and then remove and re-create mem node to the exact position before bo_pin. This can avoid breaking the data and will not cause eviction. Signed-off-by:
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pding authored
This is caused of that hypervisor fails to handle request, one known issue is MMIO unblocking timeout. In theory we can retry init here. Signed-off-by:
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pding authored
Reported-by:
Sun Gary <Gary.Sun@amd.com> Signed-off-by:
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Michel Dänzer authored
It's dead code. Signed-off-by:
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Michel Dänzer authored
Not used anymore. Signed-off-by:
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Michel Dänzer authored
Corresponding to the previous non-DC change. Signed-off-by:
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Michel Dänzer authored
Hardcoding the maximum numbers could result in spurious error messages from the IRQ state callbacks, e.g. on Polaris 11/12: [drm:dce_v11_0_set_pageflip_irq_state [amdgpu]] *ERROR* invalid pageflip crtc 5 [drm:amdgpu_irq_disable_all [amdgpu]] *ERROR* error disabling interrupt (-22) Signed-off-by:
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Harry Wentland authored
We'll need it in amdgpu_dm_mst_types.c as well. Signed-off-by:
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