- 29 Apr, 2019 6 commits
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Nicholas Kazlauskas authored
[Why] We can't do cursor programming after the planes have been disabled since there won't be any pipes - leading to lock warnings and the wrong cursor state being left in the registers. When we re-enable the planes after the previous cursor state will also remain if we don't have a cursor plane. [How] If we're disabling the planes then do the cursor programming first. If we're not disabling the planes then do the cursor programming after. Introduce the amdgpu_dm_commit_cursors helper to avoid code duplication for both of these cases. Signed-off-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by:
David Francis <David.Francis@amd.com> Acked-by:
Leo Li <sunpeng.li@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Nicholas Kazlauskas authored
[Why] The vblank and pageflip interrupts should only be enabled for a CRTC that's enabled and has active planes. The current logic takes care of this, but isn't setup to handle the case where the active plane count goes to zero but the stream remains enabled. We currently block this case since we don't allow commits that enable a CRTC with no active planes, but shouldn't be any reason we can't support this from a hardware perspective and many userspace applications expect to be able to do it (like IGT). [How] The count_crtc_active_planes function fills in the number of "active_planes" on the dm_crtc_state. This should be the same as DC's plane_count on the stream_status but easier to access since we don't need to lock the private atomic state with the DC context. Add the "interrupts_enabled" flag to the dm_crtc_state and set it based on whether the stream exists and if there are active planes on the stream. Update the disable and enable logic to make use of this new flag. There shouldn't be any functional change (yet) with this patch. Signed-off-by:
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Wentao Lou authored
amdgpu_sriov_vf would return 0x0 or 0x4 to indicate if sriov. but F32_POLL_ENABLE need 0x0 or 0x1 to determine if enabled. set 0x4 into F32_POLL_ENABLE would make SDMA0_GFX_RB_WPTR_POLL_CNTL not working. Signed-off-by:
Wentao Lou <Wentao.Lou@amd.com> Reviewed-by:
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Evan Quan authored
Update Vega20 sdma golden settings. Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
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hersen wu authored
[WHY] clock unit mis-match between caller DC and SMU interface. dc pass lock in mhz. the same unit as smu. no covert is needed. [HOW] remove covert_10k_to_mhz in smu interface this fixes corruption issue with 4k @60 display and stutter mode enable Reviewed-by:Kenneth Feng <kenneth.feng@amd.com> Signed-off-by:
hersen wu <hersenxs.wu@amd.com> Signed-off-by:
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Colin Ian King authored
Currently an allocation is being made but the allocation failure check is being performed on another pointer. Fix this by checking the correct pointer. Also use the normal kernel idiom for null pointer checks. Addresses-Coverity: ("Resource leak") Fixes: 43e3ac83 ("drm/amd/display: Add function to copy DC streams") Signed-off-by:Colin Ian King <colin.king@canonical.com> Signed-off-by:
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- 23 Apr, 2019 14 commits
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Jun Lei authored
[why] When DMCU interrupts x86, it leads to undefined phy programming [how] expand dmcu interface to support new PHY lock and unlock commands if DMCU FW doesn't support these commands, they fail silently so its okay Signed-off-by:
Jun Lei <Jun.Lei@amd.com> Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Eric Bernstein authored
[Why] Starting with DCN1, the input_pixel_processor (ipp) struct has been replaced by dpp struct (part of DAL3.1 SW architecture change). Need to update logic to handle cases where ipp is never allocated. [How] Only skip cursor position programming if both ipp and dpp resources are NULL. Signed-off-by:
Eric Bernstein <eric.bernstein@amd.com> Reviewed-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
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Aric Cyr authored
Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Reviewed-by:
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Anthony Koo authored
[Why] Power down of PHY on eDP requires us to call eDP power control to power on again [How] 1. In the case link rates don't match, disable PHY requires calling of eDP power control ON after 2. Link disable case limit to eDP path since this is not really applicable to DP since we do power down PHY as part of verify link cap 3. Move detection of eDP link settings to be done even for S4 resume cases where other dpcd cap read and edid read can be skipped Signed-off-by:
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Anthony Koo authored
[Why] Some DMCU messages were being sent in cases where there was no DMCU FW at all, which resulted in some wait timeouts [How] Delay sending some of the DMCU messages after FW init is called and DMCU is running. Signed-off-by:
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Wenjing Liu authored
We'll need the ability to copy a dc_stream_state for some features. Implement it here. Signed-off-by:
Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by:
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Anthony Koo authored
[Why] Workaround was missing in one HW disable path, meaning when all pipes are power gated, stutter was not working [How] Add workaround for init_hw path for stutter workaround Signed-off-by:
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Leo Li authored
smu.ppt_funcs is only initialized for ASICs supporting SW SMU. On a Hawaii ASIC, attempting to access the udev attribute ATTRS{power_dpm_state} will cause a null pointer deref in amdgpu_get_dpm_state() because of this. Fix by checking if SW SMU is supported first. Signed-off-by:Huang Rui <ray.huang@amd.com> Signed-off-by:
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Leo Li authored
They will be used by DC when runing ASIC-specific HUBP initialization. Signed-off-by:
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Andrey Grodzovsky authored
Patch '5edb0c9b Fix deadlock with display during hanged ring recovery' was accidentaly removed during one of DALs code merges. Signed-off-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by:
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Christian König authored
Don't block others while waiting for the fences to finish, concurrent submission is perfectly valid in this case and holding the lock can prevent killed applications from terminating. Signed-off-by:
Christian König <ckoenig.leichtzumerken@gmail.com> Reviewed-by:
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Andrey Grodzovsky authored
It's normal for VRAM to lost during GPU reset and so change the log level to INFO to avoid confusing users. Signed-off-by:
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Chengming Gui authored
enable UMDPSTATE support to force performance level for raven2. v2: squash in warning fix (Alex) Signed-off-by:
Chengming Gui <Jack.Gui@amd.com> Reviewed-by:
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Chengming Gui authored
The power profile allows the user to adjust the power state heuristics for clock level transitions. v2: squash in warning fix (Alex) Reviewed-by:
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- 19 Apr, 2019 10 commits
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Colin Ian King authored
There is a spelling mistake in a pr_err message. Fix it. Reviewed-by:
Mukesh Ojha <mojha@codeaurora.org> Signed-off-by:
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Colin Ian King authored
There is a spelling mistake in a DRM_INFO message. Fix it. Reviewed-by:
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Likun Gao authored
Enable MGCG for picasso. Signed-off-by:
Likun Gao <Likun.Gao@amd.com> Reviewed-by:
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Yintian Tao authored
Under SRIOV, we need disable DRIVER_ATOMIC. Otherwise, it will trigger WARN_ON at drm_universal_plane_init. Signed-off-by:
Yintian Tao <yttao@amd.com> Acked-by:
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wentalou authored
amdgpu_bo_destroy had a bug by calling amdgpu_bo_unref outside mutex_lock. If amdgpu_device_recover_vram executed between amdgpu_bo_unref and list_del_init, it would get NULL of shadow->parent, then caused Call Trace and GPU reset failed. Signed-off-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Leo Li authored
This is needed by DC to support EDID emulation on USB-C ports. CC: Samson Tam <Samson.Tam@amd.com> CC: Harry Wentland <harry.wentland@amd.com> CC: Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Amber Lin authored
Method of getting firmware version is the same across ASICs, so remove them from ASIC-specific files and create one in amdgpu_amdkfd.c. This new created get_fw_version simply reads fw_version from adev->gfx than parsing the ucode header. Signed-off-by:
Amber Lin <Amber.Lin@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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shaoyunl authored
Send message with parameter to SMC to set xgmi pstate Signed-off-by:
shaoyunl <shaoyun.liu@amd.com> Reviewed-by:
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Nicholas Kazlauskas authored
DC and DM already support DRM_FORMAT_RGB565, it's just missing from the list of valid formats. Cc: Harry Wentland <harry.wentland@amd.com> Cc: Leo Li <sunpeng.li@amd.com> Signed-off-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Evan Quan authored
PSP SOS firmware needs to be 0x80067 or later. Signed-off-by:
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- 15 Apr, 2019 10 commits
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Joshua Aberback authored
[Why] We used this change to investigate the performance of bandwidth validation, it will be useful to have if we need to investigate further. [How] We use performance counter tick numbers to profile performance, they live at dc->debug.bw_val_profile (set .enable in debugger to turn on measuring). Signed-off-by:
Joshua Aberback <joshua.aberback@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet Lakha@amd.com> Signed-off-by:
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Joshua Aberback authored
Add a fast_validate parameter in dc_validate_global_state for future use Signed-off-by:
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Nicholas Kazlauskas authored
[Why] As long as we have at least one non-cursor plane enabled on a CRTC then the CRTC itself can remain enabled. This will allow for commits where there's an overlay plane enabled but no primary plane enabled. [How] Remove existing primary plane fb != NULL checks and replace them with the new does_crtc_have_active_plane helper. This will be called from atomic check when validating the CRTC. Since the primary plane state can now potentially be NULL we'll need to guard for that when accessing it in some of the cursor logic. Signed-off-by:
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Nicholas Kazlauskas authored
[Why] Surface scaling info updates can affect bandwidth and blocks. We need to be checking these with global validation to avoid underflow or corruption. [How] Drop the state->allow_modeset early exit in dm_determine_update_type_for_commit. Most of those should be considered fast now anyway. Fill in scaling info and it to the surface update in atomic check. Signed-off-by:
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Nicholas Kazlauskas authored
[Why] DM thinks that the update type should be full whenever a stream or plane is added or removed (including recreations). This won't match in the case where DC thinks what looks like a fast update to DM is actually a medium or full - like scaling changes that affect bandwidth and clocks. [How] Drop this warning. DC knows better than the DM does for determining cases like this. The other warning can be kept for now since it would warn on a pretty serious DC or DM bug. Signed-off-by:
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Nicholas Kazlauskas authored
[Why] DC expects the surface memory address to identify the surface. This doesn't work with what we're doing with the temporary surfaces, it will always assume this is a full update because the surface isn't in the current context. [How] Use the surface directly. This doesn't give us much improvement yet, since we always create a new dc_plane_state when state->allow_modeset is true. The call into dc_check_update_surfaces_for_stream also needs to be locked, for two reasons: 1. It checks the current DC state 2. It modifies the surface update flags Both of which could be currently in the middle of commit work from commit tail. A TODO here is to pass the context explicitly into this function and find a way to get the surface update flags out of it without modifying the surface in place. Signed-off-by:
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Nicholas Kazlauskas authored
[Why] Planes have downscaling limits and upscaling limits per format and DM is expected to validate these using DC caps. We should fail atomic check validation if we aren't capable of doing the scaling. [How] We don't currently create store which DC plane maps to which DRM plane so we can't easily check the caps directly. For now add basic constraints that cover the absolute min and max downscale / upscale limits for most RGB and YUV formats across ASICs. Leave a TODO indicating that these should really be done with DC caps. We'll probably need to subclass DRM planes again in order to correctly identify which DC plane maps to it. Signed-off-by:
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Samson Tam authored
[Why] DM doesn't need to know which link cap is being retrieved ( verified or preferred ). Let DC figure it out. [How] Change name. Signed-off-by:
Samson Tam <Samson.Tam@amd.com> Reviewed-by:
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Nicholas Kazlauskas authored
[Why] We currently don't do DC validation for medium or full updates where the plane state isn't created. There are some medium and full updates that can cause bandwidth or clock changes to occur resulting in underflow or corruption. We need to be able to fill surface and plane info updates during atomic commit for dm_determine_update_type for commit. Since we already do this during atomic commit tail it would be good if we had the same logic in both places for creating these structures. [How] Introduce fill_dc_scaling_info and fill_dc_plane_info_and_addr. These two functions cover the following three update structures: - struct dc_scaling_info - struct dc_plane_info - struct dc_plane_address Cleanup and adapter the existing fill_plane_* helpers to work with these functions. Update call sites that used most of these sub helpers directly to work with the new functions. The exception being prepare_fb - we just want the new buffer attributes specifically in the case where we're creating the plane. This is needed for dc_commit_state in the case where the FB hasn't been previously been used. This isn't quite a refactor, but functionally driver behavior should be mostly the smae as before. The one exception is that we now check the return code for fill_plane_buffer_attributes which means that commits will be rejected that try to enable DCC with erroneous parameters. Signed-off-by:
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Nicholas Kazlauskas authored
[Why] Pitch was only calculated based on format whenever the plane state was recreated. This could result in surface corruption due to the incorrect pitch being programmed when the surface pitch changed during commits where state->allow_modeset = false. [How] Recalculate pitch at the same time we update the buffer address and other buffer attributes. This function was previously called fill_plane_tiling_attributes but I've also renamed it to fill_plane_buffer_attributes to clarify the actual intent of the function now that it's handling most buffer related attributes. Signed-off-by:
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