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  1. 09 Feb, 2007 7 commits
  3. 08 Feb, 2007 20 commits
  5. 07 Feb, 2007 13 commits
    • Kumar Gala's avatar
      [POWERPC] Fixup error handling when emulating a floating point instruction · 5fad293b
      Kumar Gala authored 
      When we do full FP emulation its possible that we need to post a SIGFPE based
on the results of the emulation.  The previous code ignored this case completely.

Additionally, the Soft_emulate_8xx case had two issues.  One, we should never
generate a SIGFPE since the code only does data movement.  Second, we were
interpreting the return codes incorrectly, it returns 0 on success, 1 on
illop and -EFAULT on a data access error.
Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
      5fad293b
    • Kumar Gala's avatar
      [POWERPC] Enable interrupts if we are doing fp math emulation · 04903a30
      Kumar Gala authored 
      Anytime we are emulating an instruction we are going to be doing some form of
get_user() to get the instruction image to decode.  Since get_user() might
sleep we need to ensure we have interrupts enabled or we might see something
like:

Debug: sleeping function called from invalid context at arch/powerpc/kernel/traps.c:697
in_atomic():0, irqs_disabled():1
Call Trace:
[D6023EB0] [C0007F84] show_stack+0x58/0x174 (unreliable)
[D6023EE0] [C0022C34] __might_sleep+0xbc/0xd0
[D6023EF0] [C000D158] program_check_exception+0x1d8/0x4fc
[D6023F40] [C000E744] ret_from_except_full+0x0/0x4c
--- Exception: 700 at 0x102a7100
    LR = 0xdb9ef04

However, we want to ensure that interrupts are disabled when handling a trap
exception that might be used for a kernel breakpoint.  This is why ProgramCheck
is marked as EXC_XFER_STD instead of EXC_XFER_EE.
Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
      04903a30
    • Kumar Gala's avatar
      [POWERPC] Added kprobes support to ppc32 · 82090035
      Kumar Gala authored 
      Added kprobes to ppc32 platforms that have use single_step_exception.  This
excludes 4xx and anything Book-E since their debug mechanisms for single stepping
are completely different.
Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
      82090035
    • Paul Mackerras's avatar
      Merge branch 'linux-2.6' · 84232005
      Paul Mackerras authored
      84232005
    • Paul Mackerras's avatar
      [POWERPC] Make pSeries use the H_BULK_REMOVE hypervisor call · f03e64f2
      Paul Mackerras authored 
      H_BULK_REMOVE lets us remove 4 entries from the MMU hash table with one
hypervisor call.  This uses it in pSeries_lpar_hpte_invalidate so we
can tear down mappings with fewer hypervisor calls.
Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      f03e64f2
    • Paul Mackerras's avatar
      [POWERPC] Clear RI bit in MSR before restoring r13 when returning to userspace · e56a6e20
      Paul Mackerras authored 
      Some instruction tracing tools use the RI (recoverable interrupt) bit
in the MSR to indicate when it's safe to single-step.  Currently we
clear RI after restoring r13 when returning to userspace.  However,
if we single-step past the point where r13 is restored, we'll corrupt
r13 in the exception entry code and not restore it.  This moves the
clearing of RI to just before r13 is restored so this doesn't happen.
Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      e56a6e20
    • Livio Soares's avatar
      [POWERPC] Fix performance monitor exception · 449d846d
      Livio Soares authored 
      To the issue: some point during 2.6.20 development, Paul Mackerras
introduced the "lazy IRQ  disabling" patch (very cool work,  BTW).
In that patch, the performance monitor unit exception was marked as
"maskable", in the sense that if interrupts were soft-disabled, that
exception could be ignored.  This broke my PowerPC profiling code.
The symptom that I see is that a varying number of interrupts
(from 0 to $n$, typically closer to 0) get delivered, when, in
reality, it should always be very close to $n$.

The issue stems from the way masking is being done.   Masking in
this fashion seems to  work well with the decrementer and external
interrupts, because they are raised again until "really"  handled.
For the PMU, however, this does not apply (at least on my Xserver
machine with a 970FX processor).  If the PMU exception is not handled,
it will _not_ be re-raised (at least on my machine).  The documentation
states that the PMXE bit in MMCR0 is set to 0 when the PMU exception
is raised.  However, software must re-set the bit to re-enable PMU
exceptions.  If the exception is ignored (as currently) not only is
that interrupt lost, but because software does not re-set PMXE, the
PMU registers are "frozen" forever.

[This patch means that performance monitor exceptions are taken and
handled even if irqs are off, as long as some other interrupt hasn't
come along and caused interrupts to be hard-disabled.  In this sense
the PMU exception becomes like an NMI.  The oprofile code for most
powerpc processors does nothing that is unsafe in an NMI context, but
the Cell oprofile code does a spin_lock_irqsave.  However, that turns
out to be OK because Cell doesn't actually use the performance
monitor exception; performance monitor interrupts come in as a
regular interrupt on Cell, so will be disabled when irqs are off.
 -- paulus.]
Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      449d846d
    • David Gibson's avatar
      [POWERPC] Compile fixes for arch/powerpc dcr code · a2c70211
      David Gibson authored 
      The new dcr code does not currently compile when configured for native
DCR access on ARCH=powerpc.  This patch fixes the problems.
Signed-off-by: default avatarDavid Gibson <dwg@au1.ibm.com>
Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      a2c70211
    • Nathan Lynch's avatar
      [POWERPC] Maple: use mmio nvram · 4297c986
      Nathan Lynch authored 
      Some systems supported by the maple platform (e.g. JS2x blades running
SLOF) are able to use the mmio_nvram backend for reading and writing
nvram.  This is an improvement over the current situation -- no nvram
access from userspace at all.

Select MMIO_NVRAM for the maple platform.

Initialize the mmio_nvram backend from maple setup code.
Signed-off-by: default avatarNathan Lynch <ntl@pobox.com>
Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      4297c986
    • Olof Johansson's avatar
      [POWERPC] pasemi: defconfig · 721e0c90
      Olof Johansson authored 
      Base pasemi defconfig. Nothing special, just the native drivers plus
common PCI-express/PCI cards.
Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      721e0c90
    • Olof Johansson's avatar
      [POWERPC] pasemi: iommu support · 31c56d82
      Olof Johansson authored 
      I/O TLB support for PA6T-1682M.
Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      31c56d82
    • Olof Johansson's avatar
      [POWERPC] pasemi: Configure DMA controller interrupts · f9fba5b7
      Olof Johansson authored 
      The DMA controller on PWRficient is somewhat special -- has a PCI header
so it looks like it's on the root PCI (-Express) root bus, but it uses
more than the default number of interrupts (and they are hardwired).

We need to wire up all interrupts for the DMA controller. The generic
IRQ code will only map the primary interrupt from the PCI header (128),
so add 129->211 by hand.
Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      f9fba5b7
    • Olof Johansson's avatar
      [POWERPC] pasemi: SMP timebase sync · c388cfeb
      Olof Johansson authored 
      Timebase update is simple on PA6T, since global updates can be done from
one core by writing to an SPR.
Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      c388cfeb
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