- 13 Jul, 2018 40 commits
-
-
Charlene Liu authored
[why] "DalEnableHDMI20" set to 0, disallow HDMI YCbCr420 and pixel clock > 340Mhz Default is enabled. Signed-off-by:
Charlene Liu <charlene.liu@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
-
Charlene Liu authored
Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
-
Leo (Sunpeng) Li authored
[Why] get_channel_status() can return 0 in returned_bytes, and report a successful operation result. This is because it prunes the first status byte out. This was preventing read_channel_reply() from being called (due to the faulty condition), and consequently preventing the AUX reply status from being set. [How] Fix the conditional so that it accounts for when get_channel_status() returns 0 bytes read. [Fixes] Fixes possible edid read failures during S3 resume, where we are now relying on DRM's DP AUX handling. This was an regression introduced by: Author: Harry Wentland <harry.wentland@amd.com> drm/amd/display: Return aux replies directly to DRM Signed-off-by:Leo (Sunpeng) Li <sunpeng.li@amd.com> Reviewed-by:
-
Leo (Sunpeng) Li authored
[Why] There is no point in keeping the AUX reply value in the raw format as returned from reading the AUX_SW_DATA register. [How] Shift it within read_channel_reply(), where the register is read, before returning it. Signed-off-by:
-
Eric Bernstein authored
v2: Remove spurious newline changes Signed-off-by:
Eric Bernstein <eric.bernstein@amd.com> Reviewed-by:
-
Jerry (Fangzhi) Zuo authored
[Why] Some monitors mark 4K@60 capable HDMI port only have 300MHz TMDS maximum, but the edid includes 4K@60 mode in cea extension block. [How] To enable 4K@60, need to limit BW by allowing YCbCr420 ONLY mode. Add YCbCr420 only support for monitors that do not fully support HDMI2.0, e.g., ASUS PA328. The YCbCr420 only support applies to DCN, DCE112 or higher. Signed-off-by:
Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com> Reviewed-by:
-
Tony Cheng authored
Signed-off-by:
Tony Cheng <tony.cheng@amd.com> Reviewed-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
-
Hersen Wu authored
bug fix: phy test PLTAT is special 80bit test pattern. The 80bit data should be hard coded within driver so that user does not need input the deata. previous driver does not have hard coded 80 bits pattern data for PLTPAT. Other than this PLTPAT, user has to input 80 bits pattern data. In case user input less than 10 bytes data, un-input data byte will be filled by 0x00. Signed-off-by:
Hersen Wu <hersenxs.wu@amd.com> Reviewed-by:
-
Yongqiang Sun authored
Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
-
Dmytro Laktyushkin authored
Signed-off-by:
-
Charlene Liu authored
Signed-off-by:
-
Charlene Liu authored
Signed-off-by:
Wesley Chalmers <Wesley.Chalmers@amd.com> Reviewed-by:
Duke Du <Duke.Du@amd.com> Acked-by:
-
Leo (Sunpeng) Li authored
GCC 4.9 reports a 'missing braces around initializer' error. This is a bug, documented here: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=53119 Fix it by adding another brace. Signed-off-by:
Mikita Lipski <Mikita.Lipski@amd.com> Acked-by:
-
Hersen Wu authored
function: get current DP PHY settings: voltage swing, pre-emphasis, post-cursor2 (defined by VESA DP specification) valid values: voltage swing: 0,1,2,3 pre-emphasis : 0,1,2,3 post cursor2 : 0,1,2,3 debugfs file phy_setings is located at /sys/kernel/debug/dri/0/DP-x there will be directories, like DP-1, DP-2,DP-3, etc. for DP display --- to figure out which DP-x is the display for DP to be check, cd DP-x ls -ll There should be debugfs file, like link_settings, phy_settings. cat link_settings from lane_count, link_rate to figure which DP-x is for display to be worked on --- to get current DP PHY settings, cat phy_settings --- to change DP PHY settings, echo <voltage_swing> <pre-emphasis> <post_cursor2> > phy_settings for examle, to change voltage swing to 2, pre-emphasis to 3, post_cursor2 to 0, echo 2 3 0 > phy_settings --- to check if change be applied, get current phy settings by cat phy_settings --- in case invalid values are set by user, like echo 1 4 0 > phy_settings HW will NOT be programmed by these settings. cat phy_settings will show the previous valid settings. Signed-off-by:
-
Hugo Hu authored
[WHY] In eDP spec, the min duration in LCDVDD on-off-on sequence should be 500ms, some BOE panels need 700ms to pass. [HOW] Add patch to wait more time when eDP power on. Signed-off-by:
Hugo Hu <hugo.hu@amd.com> Reviewed-by:
-
Dmytro Laktyushkin authored
Signed-off-by:
-
Dmytro Laktyushkin authored
Signed-off-by:
-
Dmytro Laktyushkin authored
Signed-off-by:
-
Hersen Wu authored
set PHY layer or Link layer test pattern PHY test pattern is used for PHY SI check. Link layer test will not affect PHY SI. - normal video mode 0 = DP_TEST_PATTERN_VIDEO_MODE - PHY test pattern supported 1 = DP_TEST_PATTERN_D102 2 = DP_TEST_PATTERN_SYMBOL_ERROR 3 = DP_TEST_PATTERN_PRBS7 4 = DP_TEST_PATTERN_80BIT_CUSTOM 5 = DP_TEST_PATTERN_CP2520_1 6 = DP_TEST_PATTERN_CP2520_2 = DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE 7 = DP_TEST_PATTERN_CP2520_3 - DP PHY Link Training Patterns 8 = DP_TEST_PATTERN_TRAINING_PATTERN1 9 = DP_TEST_PATTERN_TRAINING_PATTERN2 0xa = DP_TEST_PATTERN_TRAINING_PATTERN3 0xb = DP_TEST_PATTERN_TRAINING_PATTERN4 - DP Link Layer Test pattern 0xc = DP_TEST_PATTERN_COLOR_SQUARES 0xd = DP_TEST_PATTERN_COLOR_SQUARES_CEA 0xe = DP_TEST_PATTERN_VERTICAL_BARS 0xf = DP_TEST_PATTERN_HORIZONTAL_BARS 0x10= DP_TEST_PATTERN_COLOR_RAMP debugfs phy_test_pattern is located at /syskernel/debug/dri/0/DP-x --- set test pattern echo <test pattern #> > test_pattern - custom test pattern If test pattern # is not supported, NO HW programming will be done for DP_TEST_PATTERN_80BIT_CUSTOM, it needs extra 10 bytes of data for the user pattern. input 10 bytes data are separated by space echo 0x4 0x11 0x22 0x33 0x44 0x55 0x66 0x77 0x88 0x99 0xaa > test_pattern --- reset test pattern echo 0 > test_pattern --- HPD detection is disabled when set PHY test pattern when PHY test pattern (pattern # within [1,7]) is set, HPD pin of HW ASIC is disable. User could unplug DP display from DP connected and plug scope to check test pattern PHY SI. If there is need unplug scope and plug DP display back, do steps below: echo 0 > phy_test_pattern unplug scope plug DP display. "echo 0 > phy_test_pattern" will re-enable HPD pin again so that video sw driver could detect "unplug scope" and "plug DP display" Signed-off-by:
-
Dmytro Laktyushkin authored
Signed-off-by:
-
Alvin lee authored
- define new dpcd address in drm - implement new members in dpcd_caps to store values read from new dpcd address Signed-off-by:
Alvin lee <alvin.lee3@amd.com> Reviewed-by:
-
Nicholas Kazlauskas authored
- Removed dal/dm/dc loggers from linux, switched to kernel prints - Modified functions that used these directly to use macros - dc_logger support is completely dropped from Linux Signed-off-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by:
-
Harry Wentland authored
Currently we still go through DC code that does error checking, retries, etc. There's no need for that since DRM already does that for us. This simplifies the code a bit and makes it easier to debug. This also ensures we correctly tell DRM how many bytes have actually been read, as we should. This allows DRM to correctly read the EDID on the Chamelium DP port. Signed-off-by:
-
Harry Wentland authored
DRM's DP helpers take care of dealing with the error code for us. In order not to step on each other's toes we'll need to be able to simply read auch channel replies without further logic based on return values. Signed-off-by:
-
Harry Wentland authored
Access to GPIO needs to be serialized. Aux transactions are already serialized in DRM but we also need to serialize access to the GPIO pin for purposes of DP dongle detection. Call is_dp_sink_present through DM so we can lock correctly. This follows the same pattern used for DPCD transactions. Signed-off-by:
-
Tony Cheng authored
Signed-off-by:
-
Charlene Liu authored
Signed-off-by:
-
Eric Bernstein authored
Signed-off-by:
-
Hugo Hu authored
Signed-off-by:
-
Tony Cheng authored
Signed-off-by:
-
Hersen Wu authored
function description get/ set DP configuration: lane_count, link_rate, spread_spectrum valid lane count value: 1, 2, 4 valid link rate value: 06h = 1.62Gbps per lane 0Ah = 2.7Gbps per lane 0Ch = 3.24Gbps per lane 14h = 5.4Gbps per lane 1Eh = 8.1Gbps per lane debugfs is located at /sys/kernel/debug/dri/0/DP-x/link_settings --- to get dp configuration xxd -l 300 phy_settings It will list current, verified, reported, preferred dp configuration. current -- for current video mode verified --- maximum configuration which pass link training reported --- DP rx report caps (DPCD register offset 0, 1 2) preferred --- user force settings --- set (or force) dp configuration echo <lane_count> <link_rate> for example, to force to 2 lane, 2.7GHz, echo 4 0xa > link_settings spread_spectrum could not be changed dynamically. in case invalid lane count, link rate are force, no hw programming will be done. please check link settings after force operation to see if HW get programming. xxd -l 300 link_settings check current and preferred settings. Signed-off-by:
-
Tony Cheng authored
in case we have very few pins in the table, check fails and we can't boot Signed-off-by:
-
Tony Cheng authored
add generic indirect register access following our register access pattern this will make it easier to review code and programming sequence, with all the complexity hidden in macro Signed-off-by:
-
Tony Cheng authored
[WHY] we were using 6 instances based on i2caux_dce110.c [HOW] pass in how many instances to ctor Signed-off-by:
-
Charlene Liu authored
Signed-off-by:
-
Hersen Wu authored
expose dc function to be called by linux dm Signed-off-by:
-
Krunoslav Kovac authored
DCN allows cursor multiplier when blending FP16 surface. Signed-off-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
-
Eric Yang authored
[Why] Megachip dockings accesses ddc line through display driver when installing FW. Previously, we would fail every transaction because link attached to mst branch did not have their ddc transaction type set. [How] Set ddc transaction type when mst branch is connected. Signed-off-by:
Eric Yang <Eric.Yang2@amd.com> Reviewed-by:
-
Tony Cheng authored
Signed-off-by:
-
Eric Bernstein authored
Separate HUBP surface size and rotation/mirror programming so that HUBP revision without mirror/rotation do not access those register fields. Signed-off-by:
-
