1. 22 Sep, 2011 5 commits
    • nagalakshmi.nandigama@lsi.com's avatar
      [SCSI] mpt2sas: Added NUNA IO support in driver which uses multi-reply queue support of the HBA · 911ae943
      nagalakshmi.nandigama@lsi.com authored
      Support added for controllers capable of multi reply queues.
      
      The following are the modifications to the driver to support NUMA.
      
      1) Create the new structure adapter_reply_queue to contain the reply queue
         info for every msix vector.  This object will contain a
         reply_post_host_index, reply_post_free for each instance, msix_index, among
         other parameters.  We will track all the reply queues on a link list called
         ioc->reply_queue_list. Each reply queue is aligned with each IRQ, and is
         passed to the interrupt via the bus_id parameter.
      
      (2) The driver will figure out the msix_vector_count from the PCIe MSIX
          capabilities register instead of the IOC Facts->MaxMSIxVectors. This is
          because the firmware is not filling in this field until the driver has
          already registered MSIX support.
      
      (3) If the ioc_facts reports that the controller is MSIX compatible in the
          capabilities, then the driver will request for multiple irqs.  This count
          is calculated based on the minimum between the online cpus available and
          the ioc->msix_vector_count.  This count is reported to firmware in the
          ioc_init request.
      
      (4) New routines were added _base_free_irq and _base_request_irq, so
          registering and freeing msix vectors were done thru simple function API.
      
      (5) The new routine _base_assign_reply_queues was added to align the msix
          indexes across cpus. This will initialize the array called
          ioc->cpu_msix_table.  This array is looked up on every MPI request so the
          MSIxIndex is set appropriately.
      
      (6) A new shost sysfs attribute was added to report the reply_queue_count.
      
      (7) User needs to set the affinity cpu mask, so the interrupts occur on the
          same cpu that sent the original request.
      Signed-off-by: default avatarNagalakshmi Nandigama <nagalakshmi.nandigama@lsi.com>
      Signed-off-by: default avatarJames Bottomley <JBottomley@Parallels.com>
      911ae943
    • Moger, Babu's avatar
      [SCSI] scsi_dh_rdac: Adding couple more vendor product ids · 66195fc9
      Moger, Babu authored
      This patch adds couple more Vendor/Product IDs for RDAC.. There are no
      functional changes.
      Signed-off-by: default avatarBabu Moger <babu.moger@netapp.com>
      Signed-off-by: default avatarJames Bottomley <JBottomley@Parallels.com>
      66195fc9
    • Dan Williams's avatar
      [SCSI] isci: initial sgpio write support · ad4f4c1d
      Dan Williams authored
      Basic support to initialize the gpio unit, accept an incomming
      SAS_GPIO_REG_TX_GP bitstream, and translate it to the ODx.n fields in
      the hardware registers.  If register indexes outside the supported range
      are specified in the SMP frame we simply accept the write and return how
      many registers (SFF-8485) were written (libsas reports this as residue
      in the request).
      Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
      Signed-off-by: default avatarJames Bottomley <JBottomley@Parallels.com>
      ad4f4c1d
    • Dan Williams's avatar
      [SCSI] isci: fix sgpio register definitions · 13257cfb
      Dan Williams authored
      output_data_select registers are off by one u32
      
      delete the macros we will never use.
      Reported-by: default avatarArtur Wojcik <artur.wojcik@intel.com>
      Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
      Signed-off-by: default avatarJames Bottomley <JBottomley@Parallels.com>
      13257cfb
    • Dan Williams's avatar
      [SCSI] libsas: sgpio write support · 8ec6552f
      Dan Williams authored
      Add SFF-8485 v0.7 / SAS-1 smp-write-gpio register support to libsas.
      Defer SAS-2 support unless/until it defines an sgpio interface.
      
      Minimum implementation needed to get the lights blinking.
      try_test_sas_gpio_gp_bit() provides a common method to parse the
      incoming write data (raw bitstream), and the to_sas_gpio_gp_bit() helper
      routine can be used as a basis for the set/clear operations for the
      'read' implementation.  Host implementations parse as many bits
      (ODx.[012]) as are locally supported and report the number of registers
      successfully written.  If the submitted data overruns the internal
      number of registers available report the write as a success with the
      number of bytes remaining reported in ->resid_len.
      
      Example (assuming an active backplane) set the "identify" pattern for
      the first 21 devices:
      
      smp_write_gpio --count=2 --data=92,49,24,92,24,92,49,24 -t 4 --index=1 /dev/bsg/sas_hostX
      Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
      Signed-off-by: default avatarJames Bottomley <JBottomley@Parallels.com>
      8ec6552f
  2. 18 Sep, 2011 1 commit
  3. 17 Sep, 2011 8 commits
  4. 30 Aug, 2011 10 commits
  5. 29 Aug, 2011 16 commits