- 31 Oct, 2013 16 commits
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Ulf Hansson authored
Suspend and resume of cards are handled by the protocol layer and consequently the mmc_suspend|resume_host APIs are marked as deprecated. While moving away from using the deprecated APIs, there are nothing left to be done for the suspend and resume callbacks, so remove them. Cc: Ludovic Desroches <ludovic.desroches@atmel.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org> Acked-by:
Ludovic Desroches <ludovic.desroches@atmel.com> Signed-off-by:
Chris Ball <cjb@laptop.org>
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Ulf Hansson authored
We want to give user space provision to fully consume a card insert/remove event, when the event was caused by a wakeup irq. By signaling the wakeup event for a time of 5 s for devices configured as wakeup capable, we likely will be prevent a sleep long enough to let user space consume the event. To enable this feature, host drivers must thus configure their devices as wakeup capable. This is a reworked implementation of the old wakelocks for the mmc subsystem, originally authored by Colin Cross and San Mehat for the Android kernel. Zoran Markovic shall also be given cred for recently re-trying to upstream this feature. Cc: San Mehat <san@google.com> Cc: Colin Cross <ccross@android.com> Cc: John Stultz <john.stultz@linaro.org> Cc: Zoran Markovic <zoran.markovic@linaro.org> Signed-off-by:
Zoran Markovic <zoran.markovic@linaro.org> Signed-off-by:
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Ulf Hansson authored
Since mmc_select_voltage now only gets called from the attach sequence, it makes sense to move the out of spec validations of the card ocr into this function. Signed-off-by:
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Ulf Hansson authored
According to eMMC/SD/SDIO specs, the VDD (VCC) voltage level must be maintained during the initialization sequence. If we want/need to tune the voltage level, a complete power cycle of the card must be executed. Most host drivers conforms to the specifications by only allowing to change VDD voltage level at the MMC_POWER_UP state, but some also cares about MMC_POWER_ON state, which they should'nt. This patch will not break those drivers, but they could clean up code to better reflect what is expected from the protocol layer. A big re-work of the mmc_select_voltage function is done to only change VDD voltage level if the host supports MMC_CAP2_FULL_PWR_CYCLE. Otherwise only validation of the host and card ocr mask will be done. A very nice side-effect of this patch is that we now don't need to reset the negotiated ocr mask at the mmc_power_off function, since now it will actually reflect the present voltage level, which safely can be used at the next power up and re-initialization. Moreover, we then only need to execute mmc_select_voltage from the attach sequence. Signed-off-by:
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Ulf Hansson authored
The negotiated ocr mask is directly related to the card. Once a card gets removed, the mask shall be dropped. By moving the cache of the ocr mask from the host struct to the card struct we have accomplished this. Signed-off-by:
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Ulf Hansson authored
At several places in mmc_sdio_init_card function the cached mask in host->ocr were being updated. To simplify code, we make use of an local ocr parameter instead. Signed-off-by:
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Ulf Hansson authored
The retry and fallback mechanism when failing to switch to 1.8V signaling voltage is handled by the SDIO card init function. Thus we can remove the duplicated old code from the attach function. Signed-off-by:
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Ulf Hansson authored
This is yet another step of restructure code to be able to fixup the setup of the negotiated ocr mask. Signed-off-by:
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Ulf Hansson authored
As a step to fixup the setup of the negotiated ocr mask, we need the mmc_power_up|cycle functions to take the ocr as a parameter. Signed-off-by:
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Ulf Hansson authored
Some switch operations like poweroff notify, shall according to the spec not be followed by any other new commands. For these cases and when the host does'nt support MMC_CAP_WAIT_WHILE_BUSY, we must not send status commands to poll for busy detection. Instead wait for the stated timeout from the EXT_CSD before completing the request. Signed-off-by:
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Eric Ernst authored
This patch adds intel_mid clovertrail SDIO and eMMC device IDs to the sdhci-pci driver. Signed-off-by:
Eric Ernst <eric.ernst@linux.intel.com> Signed-off-by:
David Cohen <david.a.cohen@linux.intel.com> Signed-off-by:
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Balaji T K authored
With lazy disable gone, no_off is not used any more in omap_hsmmc Signed-off-by:
Balaji T K <balajitk@ti.com> Signed-off-by:
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Balaji T K authored
clock divisor can take a max value of 1023. Update code so that card init can be handled at f_min even at higher IP clock frequencies from which clock to the card is derived. Signed-off-by:
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Jianpeng Ma authored
With HSMMC_HAS_UPDATED_RESET reset of cmd/data (SRC/SRD) can be to quick and can be missed resulting in wait for software timeout. With cpu_relax timeout can be long and unpredictable. Use udelay instead for timeout implementation. Reported-by:
Yuzheng Ma <mayuzheng@kedacom.com> Tested-by:
Hein Tibosch <hein_tibosch@yahoo.es> Signed-off-by:
Jianpeng Ma <majianpeng@gmail.com> Signed-off-by:
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Tony Lindgren authored
We want to get rid of the omap specific platform init code callbacks as they don't play nice with device tree. Convert the context loss check to be based on a register state detection instead. Cc: Andreas Fenkart <afenkart@gmail.com> Signed-off-by:
Tony Lindgren <tony@atomide.com> [add check for CON and HCTL in context save and restore function] Signed-off-by:
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Balaji T K authored
pbias_disable is set to protect the mmc pbias i/o cells in DT boot by preventing voltage switch. Currently pbias_disable is enabled only for omap3 and not for omap4 due to reg_offset difference of 0x100. Enable pbias_disable for omap4+ too by using res->start which does not include the reg_offset. Signed-off-by:
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- 21 Oct, 2013 15 commits
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Dong Aisheng authored
Remove unneeded call of call sdhci_enable_preset_value when having SDHCI_QUIRK2_PRESET_VALUE_BROKEN. Signed-off-by:
Dong Aisheng <b29396@freescale.com> Acked-by:
Shawn Guo <shawn.guo@linaro.org> Signed-off-by:
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Dong Aisheng authored
The i.MX6 does not support preset value feature. Signed-off-by:
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Dong Aisheng authored
The imx6q/dl supports SDR50 tunning, enable it for a better timing on SDR50 mode. Signed-off-by:
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Dong Aisheng authored
The DLL(Delay Line) is newly added to assist in sampling read data. The DLL provides the ability to programmatically select a quantized delay (in fractions of the clock period) regardless of on-chip variations such as process, voltage and temperature (PVT). This patch adds a user interface to set slave delay line via device tree. It's usually used in high speed mode like mmc DDR mode when the signal quality is not good caused by board design, e.g. the signal path is too long. User can manually set delay line to find a suitable data sampling window for card to work properly. Signed-off-by:
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Dong Aisheng authored
When DDR mode is enabled, the initial pre_div should be 2. And the pre_div value should be changed accordingly from ... 02h) Base clock divided by 4 01h) Base clock divided by 2 00h) Base clock divided by 1 to .. 02h) Base clock divided by 8 01h) Base clock divided by 4 00h) Base clock divided by 2 Signed-off-by:
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Dong Aisheng authored
The original code missed to report an error when the maximum tuning loops exhausted or timeout, it will cause the upper layer to wrongly think the tuning process is passed. Signed-off-by:
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Dong Aisheng authored
When reading CAP_1 register for mx6sl, ignore bit[0-15] as it stores CAP_2 register value which is new introduced in mx6sl. Without this fix, the max clock for mx6sl may not be correct since it's wrongly calculated by reading CAP_1 register. Signed-off-by:
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Dong Aisheng authored
The mx6sl supports standard sdhci tuning, then esdhc_executing_tuning is only needed for mx6q/dl. We introduce is_imx6_usdhc() and is_imx6sl_usdhc() to handle the difference. The standard tuning is enabled by setting ESDHC_TUNE_CTRL_STD_TUNING_EN bit in new register ESDHC_TUNE_CTRL and operates with new tuning bits defined in SDHCI_ACMD12_ERR register. Note: mx6sl can also work on the old manually tuning mode as mx6q/dl if not enable standard tuning mode. Signed-off-by:
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Shawn Guo authored
Create a struct esdhc_soc_data with moving 'flags' field from pltfm_imx_data into it, and pass the pointer of this SoC specific data structure through of_device_id.data directly, so that the translation from enum imx_esdhc_type to flags can be saved. With the change, enum imx_esdhc_type can be eliminated, since we can implement the is_imx*_esdhc() by checking the esdhc_soc_data pointer. The unused is_imx35_esdhc() and is_imx51_esdhc() are also removed, and the others are kept there as we will need to use them to handle some small register differences later, where use of new flags might be a little overkilled. Signed-off-by:
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Shawn Guo authored
As a good practice, device driver should not modify pdev->id_entry but keep it immutable. Let's assign of_device_id.data with imx_esdhc_type constants directly, so that we do not have to manipulate pdev->id_entry in .probe(). As the result, sdhci-esdhc-imx53 and sdhci-usdhc-imx6q can be removed from platform_device_id table now, since they will only probe from device tree. Signed-off-by:
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Shawn Guo authored
Add flag ESDHC_FLAG_USDHC to tell that the ESDHC is actually an USDHC block, and replace the is_imx6q_usdhc() occurrences with inline function esdhc_is_usdhc() which checks the flag. Signed-off-by:
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Shawn Guo authored
Just like the use of the flag ESDHC_FLAG_MULTIBLK_NO_INT, let's add another flag ESDHC_FLAG_ENGCM07207 to enable the workaround for errata ENGcm07207 and set the flag for i.MX25 and i.MX35 ESDHC. While at it, let's use BIT() macro for ESDHC_FLAG_MULTIBLK_NO_INT as well. Signed-off-by:
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Sonic Zhang authored
The DMA operation in SDIO CMD53 may fail because the 4 bit SDIO mode is not set up correctly on BF548. Remove 2 blank lines as well. Signed-off-by:
Sonic Zhang <sonic.zhang@analog.com> Signed-off-by:
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Axel Lin authored
Simplify the code to set/clear BM_SD_OFF bit: | power_inverted: 0 | power_inverted: 1 ------------------------------------------------- enable: 0 | SET BM_SD_OFF | CLEAR BM_SD_OFF ------------------------------------------------- enable: 1 | CLEAR BM_SD_OFF | SET BM_SD_OFF Signed-off-by:Axel Lin <axel.lin@ingics.com> Acked-by:
Tony Prisk <linux@prisktech.co.nz> Signed-off-by:
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David Cohen authored
Implement initial SDHCI Intel Merrifield support. This patch is based on previous one from Yunpeng Gao <yunpeng.gao@intel.com>. Signed-off-by:
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- 27 Sep, 2013 1 commit
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Dong Aisheng authored
This enables access the actual_clock via sys. root@imx6qsabreauto:~# cat /sys/kernel/debug/mmc0/ios clock: 198000000 Hz actual clock: 198000000 Hz vdd: 17 (2.9 ~ 3.0 V) bus mode: 2 (push-pull) chip select: 0 (don't care) power mode: 2 (on) bus width: 2 (4 bits) timing spec: 6 (sd uhs SDR104) signal voltage: 0 (1.80 V) Signed-off-by:
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- 26 Sep, 2013 8 commits
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Dong Aisheng authored
According to spec, the pre_div for imx6q should be 1, or the biggest clock rate we can get is a half of host clock rate. This may cause we can not get the proper clock rate as we want. e.g. if the desired clock is 200Mhz, however, the host clock is 200Mhz too, then it causes the actual clock we get is 100Mhz due to pre_div is 2. Signed-off-by:
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Dong Aisheng authored
Without proper pinctrl state, the card may not be able to work on high speed stablely. e.g. SDR104. This patch add pinctrl state switch code according to different uhs mode include 100mhz sate, 200mhz sate and normal state (50Mhz and below). Signed-off-by:
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Dong Aisheng authored
Freescale i.MX6Q/DL uSDHC clock tuning progress is a little different from the standard tuning process defined in host controller spec v3.0. Thus we use platform_execute_tuning instead of standard sdhci tuning. The main difference are: 1) not only generate Buffer Read Ready interrupt when tuning is performing. It generates all other DATA interrupts like the normal data command. 2) SDHCI_CTRL_EXEC_TUNING is not automatically cleared by HW, instead it's controlled by SW. 3) SDHCI_CTRL_TUNED_CLK is not automatically set by HW, it's controlled by SW. 4) the clock delay for every tuning is set by SW. Signed-off-by:
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Dong Aisheng authored
The signal voltage switch flow requires to shutdown and output clock in a specific sequence according to standard host controller v3.0 spec. In that timing, the card must really receive clock or not. However, for i.MX6Q, the uSDHC will not output clock even the clock is enabled until there is command or data in transfer on the bus, which will then cause singal voltage switch always to fail. For i.MX6Q, we clear ESDHC_VENDOR_SPEC_FRC_SDCLK_ON bit to let controller to gate off clock automatically and set that bit to force clock output if clock is on. This is required by SD3.0 support. Signed-off-by:
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Dong Aisheng authored
We need a lot of imx6 specific things into common esdhc_set_clock for support SD3.0 and eMMC DDR mode which is not needed for power pc platforms, so esdhc_set_clock seems not so common anymore. Instead of keeping add platform specfics things into this common API, we choose to move that code into platform driver itself to handle. This can also exclude the dependency between imx and power pc on this headfile and is easy for maintain in the future. Signed-off-by:
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Dong Aisheng authored
It helps for platform code to use it send tuning commands. Signed-off-by:
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Dong Aisheng authored
The tuning of some platforms may not follow the standard host control spec v3.0, e.g. Freescale uSDHC on i.MX6Q/DL. Add a hook here to allow execute platform specific tuning instead of standard host controller tuning. The hook only replaces the tuning process, so it's placed after tuning checking and before the real tuning process. Some notes for the tuning hook: 1) it needs handle lock itself if it wants to access host controller according platform specific implementation. 2) do not need to handle runtime pm since it executes with runtime pm get already. Signed-off-by:
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Axel Lin authored
This avoid duplicated implementation. Signed-off-by:
Stephen Warren <swarren@wwwdotorg.org> Signed-off-by:
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