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  1. 28 May, 2014 4 commits
  3. 26 May, 2014 1 commit
  5. 21 May, 2014 14 commits
  7. 20 May, 2014 9 commits
  9. 12 May, 2014 4 commits
  11. 09 May, 2014 1 commit
    • Brian Norris's avatar
      mtd: nand: refactor erase_cmd() to return chip status · 49c50b97
      Brian Norris authored 
      The nand_chip::erase_cmd callback previously served a dual purpose; for
one, it allowed a per-flash-chip override, so that AG-AND devices could
use a different erase command than other NAND. These AND devices were
dropped in commit 14c65786 (mtd: nand:
remove AG-AND support). On the other hand, some drivers (denali and
doc-g4) need to use this sort of callback to implement
controller-specific erase operations.

To make the latter operation easier for some drivers (e.g., ST's new BCH
NAND driver), it helps if the command dispatch and wait functions can be
lumped together, rather than called separately.

This patch does two things:
 1. Pull the call to chip->waitfunc() into chip->erase_cmd(), and return
    the status from this callback
 2. Rename erase_cmd() to just erase(), since this callback does a
    little more than just send a command
Signed-off-by: default avatarBrian Norris <computersforpeace@gmail.com>
Tested-by: default avatarLee Jones <lee.jones@linaro.org>
      49c50b97
  13. 29 Apr, 2014 1 commit
  15. 18 Apr, 2014 1 commit
  17. 17 Apr, 2014 3 commits
    • Brian Norris's avatar
      Merge branch 'spinor' · d66d3519
      Brian Norris authored 
      Addition of the spi-nor framework, plus updates to the ST SPI FSM
driver.
      d66d3519
    • Brian Norris's avatar
      mtd: st_spi_fsm: only build for ARM · dc002f99
      Brian Norris authored 
      COMPILE_TEST allows us to build this driver on other arch'es. But not
all arch'es have the right I/O accessors -- particularly, x86 is missing
readsl() and writesl().

So just restrict this driver to ARCH_STI. It's still buildable for a
multiplatform ARM kernel, so it can get decent compile coverage.
Signed-off-by: default avatarBrian Norris <computersforpeace@gmail.com>
Acked-by: default avatarLee Jones <lee.jones@linaro.org>
      dc002f99
    • Brian Norris's avatar
      mtd: st_spi_fsm: correct type issues · 38e2eee9
      Brian Norris authored 
      Compile-testing for a 64-bit arch uncovers several bad casts:

    In file included from include/linux/linkage.h:4:0,
                     from include/linux/kernel.h:6,
                     from drivers/mtd/devices/st_spi_fsm.c:15:
    drivers/mtd/devices/st_spi_fsm.c: In function ‘stfsm_read_fifo’:
    drivers/mtd/devices/st_spi_fsm.c:758:11: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
      BUG_ON((((uint32_t)buf) & 0x3) || (size & 0x3));
    ...

Use uintptr_t instead of uint32_t, since it's guaranteed to be
pointer-sized.

We also see this warning, if size_t is not 32 bits wide:

    In file included from drivers/mtd/devices/st_spi_fsm.c:15:0:
    drivers/mtd/devices/st_spi_fsm.c: In function ‘stfsm_mtd_write’:
    include/linux/kernel.h:712:17: warning: comparison of distinct pointer types lacks a cast [enabled by default]
      (void) (&_min1 == &_min2);  \
                     ^
    drivers/mtd/devices/st_spi_fsm.c:1704:11: note: in expansion of macro ‘min’
       bytes = min(FLASH_PAGESIZE - page_offs, len);
               ^

Just use min_t() to force the type conversion, since we don't really
want to upgrade 'page_offs' and 'bytes' to size_t; they only should be
handling <= 256 byte offsets.
Signed-off-by: default avatarBrian Norris <computersforpeace@gmail.com>
Acked-by: default avatarLee Jones <lee.jones@linaro.org>
      38e2eee9
  19. 16 Apr, 2014 2 commits
    • Brian Norris's avatar
      mtd: fsl-quadspi: fix __iomem annotations · a965d04c
      Brian Norris authored 
      This corrects some sparse warnings:

   drivers/mtd/spi-nor/fsl-quadspi.c:281:31: warning: incorrect type in initializer (different address spaces) [sparse]
   drivers/mtd/spi-nor/fsl-quadspi.c:281:31:    expected void *[noderef] <asn:2>base [sparse]
   drivers/mtd/spi-nor/fsl-quadspi.c:281:31:    got void [noderef] <asn:2>*iobase [sparse]
   (etc.)
Signed-off-by: default avatarBrian Norris <computersforpeace@gmail.com>
Acked-by: default avatarHuang Shijie <b32955@freescale.com>
      a965d04c
    • Huang Shijie's avatar
      mtd: gpmi: add gpmi_devdata{} to simplify the code · 6189cccb
      Huang Shijie authored 
      More and more chips use the GPMI controller, but these chips may use different
version of the IPs for GPMI and BCH. Different IPs have
 different features, such as the BCH's maximum ECC strength:

     imx23/imx28 -- the BCH's maximum ECC strength is 20
     imx6q       -- the BCH's maximum ECC strength is 40
     imx6sx      -- the BCH's maximum ECC strength is 62

This patch does the following things:

  [1] add a new data structure, gpmi_devdata{}, to store the information for
      each IP. Besides the IP version, we store the following information:
         <1> BCH's maximum ECC strength.
         <2> the maximum chain delay in ns used by the EDO mode.

      but we may add more information in future.

  [2] add the gpmi_devdata_imx{23|28|6q} to replace the gpmi_ids.

  [3] simplify the code by using the ECC strength from gpmi_devdata, such as
      gpmi_check_ecc() and legacy_set_geometry();

  [4] use the maximum chain delay to initialize the EDO mode,
      see gpmi_compute_edo_timing().

  [5] rewrite the macros, such GPMI_IS_MX{23|28|6Q}.
Signed-off-by: default avatarHuang Shijie <b32955@freescale.com>
Signed-off-by: default avatarBrian Norris <computersforpeace@gmail.com>
      6189cccb
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