- 07 Jul, 2011 40 commits
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Fabio Estevam authored
Signed-off-by:
Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by:
Sascha Hauer <s.hauer@pengutronix.de>
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Fabio Estevam authored
Signed-off-by:
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by:
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Shawn Guo authored
The patch adds following configurations to enable build of mx23evk and mx28evk in defconfig. CONFIG_MACH_MX23EVK CONFIG_MACH_MX28EVK Signed-off-by:
Shawn Guo <shawn.guo@linaro.org> Signed-off-by:
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Sascha Hauer authored
Conflicts: arch/arm/mach-imx/mach-mx31_3ds.c arch/arm/mach-imx/mach-scb9328.c Signed-off-by: -
Sascha Hauer authored
CONFIG_ARCH_* are deprecated, so remove one user. Signed-off-by: -
Fabio Estevam authored
On the i.MX SPI driver the chipselect pins can be of the following types: - internal: when the chipselect pin is used as a dedicated CS pin of the CSPI controller - GPIO: a generic GPIO can be used as a chipselect funtion On the mx27_3ds the SPI2 chip select is a GPIO, so don't annotate 'internal' in the chip select definition. Signed-off-by:
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Fabio Estevam authored
Use the standard gpio_to_irq function instead of a dedicated IRQ_GPIOx macro. Signed-off-by:
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Fabio Estevam authored
Place the UART gpio initialization inside the scb9328_init function as it is done on other i.MX boards. Signed-off-by:
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H Hartley Sweeten authored
Signed-off-by:
H Hartley Sweeten <hsweeten@visionengravers.com> Cc: Sascha Hauer <kernel@pengutronix.de> Signed-off-by:
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Fabio Estevam authored
As no flag is passed into UART0 platform data, pass NULL argument when registering UART0. Signed-off-by:
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Sascha Hauer authored
There are several occurences where MXC_INTERNAL_IRQ is assumed to be the start of the gpio interrupts. It was never meant this way. Replace these with gpio_to_irq. Signed-off-by:
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Sascha Hauer authored
This becomes meaningless in subsequent patches. Signed-off-by: -
Sascha Hauer authored
This becomes meaningless in subsequent patches. Signed-off-by: -
Sascha Hauer authored
CONFIG_ARCH_* are deprecated, so remove one user. Signed-off-by: -
Sascha Hauer authored
since we now can include all soc specific headers at once we do not need the ifdeffery anymore. Signed-off-by: -
Sascha Hauer authored
All soc specific header have proper namespace now and thus can be included at once. Signed-off-by: -
Sascha Hauer authored
We have a clocksource which renders CLOCK_TICK_RATE useless. Define it to a bogus value to get rid of some ifdeffery. Signed-off-by: -
Sascha Hauer authored
Signed-off-by: -
Uwe Kleine-König authored
This allows to move the led definition to .init.rodata. Signed-off-by:
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Uwe Kleine-König authored
This gets rid of per machine struct platform_device definitions and allows to move the platform data and led definition to .init.rodata. Signed-off-by:
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Uwe Kleine-König authored
This gets rid of per machine struct platform_device definitions and allows to move the platform data and led definition to .init.rodata. Signed-off-by:
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Fabio Estevam authored
Instead of using gpio_request followed by gpio_direction_output use gpio_request_array when requesting multiple pins. Also fixed the location of the delay for the reset and make the BABBAGE_USB_PHY_RESET to toggle. Signed-off-by:
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Fabio Estevam authored
The USB PHY Reset GPIO can be configured in the same place as the other GPIOs. While at it rename the pin as BABBAGE_USB_PHY_RESET to make clearer its purpose. Signed-off-by:
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Troy Kisky authored
", o" was used for ", 0" ", 17" was used for ", 7 | 0x10" Signed-off-by:
Troy Kisky <troy.kisky@boundarydevices.com> Signed-off-by:
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Sascha Hauer authored
dmaengine expects the maxburst parameter in words, not bytes. The imxdma driver and its users do this wrong. Fix this. As a side note the imx-pcm-dma-mx2 driver was 'fixed' to work with imx-dma. This broke the driver with imx-sdma support which correctly takes the maxburst parameter in words. This patch puts the sdma based sound back to work. Signed-off-by: -
Lothar Waßmann authored
The clock from which the I2C timing is derived is the ipg_perclk not ipg_clk. I2C bus frequency was lower by a factor of ~8 due to the clock divider calculation being based on 66.5MHz IPG clock while the bus actually uses 8MHz ipg_perclk. Kernel version: 3.0.0-rc2 branch 'imx-for-next' of git://git.pengutronix.de/git/imx/linux-2.6Signed-off-by:
Lothar Waßmann <LW@KARO-electronics.de> Signed-off-by:
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Uwe Kleine-König authored
The pins are actually used (not in mainline yet): D4 -> SSP2_D0 D5 -> GPIO D6 -> GPIO D7 -> GPIO for owire so their pinmapping for SSP0 is wrong. Signed-off-by:
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Axel Lin authored
Fix below build error: CC arch/arm/mach-mxs/devices/platform-mxsfb.o arch/arm/mach-mxs/devices/platform-mxsfb.c: In function 'mx23_add_mxsfb': arch/arm/mach-mxs/devices/platform-mxsfb.c:27: error: implicit declaration of function 'DMA_BIT_MASK' make[2]: *** [arch/arm/mach-mxs/devices/platform-mxsfb.o] Error 1 make[1]: *** [arch/arm/mach-mxs/devices] Error 2 make: *** [arch/arm/mach-mxs] Error 2 Signed-off-by:
Axel Lin <axel.lin@gmail.com> Tested-by:
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Fabio Estevam authored
Mark the actual interrupt source for some interrupts currently marked as reserved. Signed-off-by:
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Troy Kisky authored
iomux-v3.c uses NO_PAD_CTRL as a 32 bit value so it should not be shifted left by MUX_PAD_CTRL_SHIFT(41) Previously, anything requesting NO_PAD_CTRL would get their pad control register set to 0. Since it is a pad control mask, place it with the other mask values. Signed-off-by:
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Fabio Estevam authored
On MX51 the address space length for SSI is 16KB. Signed-off-by:
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Shawn Guo authored
The imx25 sdma script only gets TO1 version, so there is no need to encode "to1" in the variable name. Signed-off-by:
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Shawn Guo authored
The value 0 is not a valid TO version number. With the current code, imx-sdma driver will try to load firmware sdma-imx25-to0.bin, which is obviously not a good name. Instead, sdma-imx25-to1.bin makes much more sense. Signed-off-by:
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Shawn Guo authored
The sdma on soc imx25 is not a V1 but V2 block. Signed-off-by:
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Shawn Guo authored
The sdma on all imx soc gets 16K IO space not 4K. Signed-off-by:
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Fabio Estevam authored
Fix the following warning: CC arch/arm/plat-mxc/iomux-v1.o arch/arm/plat-mxc/iomux-v1.c: In function 'mxc_gpio_setup_multiple_pins': arch/arm/plat-mxc/iomux-v1.c:160: warning: 'ret' may be used uninitialized in this function arch/arm/plat-mxc/iomux-v1.c:160: note: 'ret' was declared here Signed-off-by:
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Fabio Estevam authored
Fix the 2.8V (VMMC1) and 1.8V (VGEN) voltage generation on mx27_3ds. Also configure the IOMUX for the PMIC interrupt pin and for the CSPI chip select that is connected to the MC13783 PMIC. In order to get the voltage for the LCD (2.8V and 1.8V) it is also necessary to turn on GPO1 and GPO3 supplies because they are connected to switches that enable these two voltages. Signed-off-by:
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Fabio Estevam authored
When setting the IOMUX of multiple pins via mxc_gpio_setup_multiple_pins, gpio_request is called and this prevents subsequent calls of gpio_request done by drivers to succeed. Remove gpio_request call from mxc_gpio_setup_multiple_pins function. As gpio_request is removed from mxc_gpio_setup_multiple_pins, there is no need to have mxc_gpio_release_multiple_pins anymore, so remove this function. Tested on a mx27_3ds board and after applying this patch it is possible to define all the IOMUX setup in a static array Signed-off-by:
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Fabio Estevam authored
Original code was assuming that the CSPI1 pins on the MX31PDK were the primary pin function, which is incorrect. On MX31PDK board these are the pins that provide CSPI1 functionality: DSR_DCE1 (ALT mode 1) --> CSPI1_CLK RI_DCE1 (ALT mode 1) --> CSPI1_RDY DTR_DTE1 -->CSI1_MOSI DSR_DTE1 --> CSPI1_MISO DTR_DCE2 ---> CSPI1_SS2 The 3 IOMUX settings above are done via GPR as per Table A-1 of the MX31RM. This patch fixes the CSPI1 IOMUX and makes the LCD to be functional. Signed-off-by:
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Fabio Estevam authored
Signed-off-by:
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