- 21 Oct, 2017 39 commits
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Tony Cheng authored
experimental change for testing if max line buffer result in better stutter efficiency for 1080p, LB can hold up to 9 line at 10bpcc, potentially add 10 line time of latency hiding. Signed-off-by:
Tony Cheng <tony.cheng@amd.com> Reviewed-by:
Yongqiang Sun <yongqiang.sun@amd.com> Acked-by:
Harry Wentland <Harry.Wentland@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Tony Cheng authored
1. reverts commit e67f51012740 ("dc: temp disable DCC on high res.") - default still DCC enabled 2. add debug options to decide how DCC is disabled - disable DCC - disable DCC if DCC requires 128b (aka. half) request -- observed compressed data corruption result in screen corruption in full (256b) request while half (128b) would cause DCN to hang, result in DF hang Signed-off-by: -
Tony Cheng authored
also refactor debug option. now pipe_split_policy are dynamic = no hack around dcn_calcs. will split based on HW recommendation avoid = avoid split if we can support the config with higher voltage avoid_multi_display = allow split with single display output. force_single_disp_pipe_split force single display to pipe split to improve stutter efficiency by using DET buffers using 2 HUBP. Signed-off-by:
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Charlene Liu authored
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Charlene Liu <charlene.liu@amd.com> Reviewed-by:
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Jerry Zuo authored
In SST daisy chain scenario, edid is getting read in mst hotplug routine. It is getting conflict with drm send_enum_path_resources kernel thread in terms of i2c bus which is getting locked up in such case. Have edid being read in get_mode hook, instead of in hotplug routine. Signed-off-by:
Jerry Zuo <Jerry.Zuo@amd.com> Reviewed-by:
Roman Li <Roman.Li@amd.com> Acked-by:
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Yongqiang Sun authored
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Yongqiang Sun authored
In case of two monitor connected and turn off one of the monitors, OTG0 is locked after graphic plane off due to redundant programming front end regs. Signed-off-by:
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SivapiriyanKumarasamy authored
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SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com> Reviewed-by:
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Wenjing Liu authored
[Description] link type is not updated before mst topology discovery. This causes issue when branch device response to link address after before the start topology discovery event finishes. [Solution] update link type to mst before topology discovery Signed-off-by:
Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by:
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Eric Yang authored
When doing SLS, KMD gives us clipped v_addressable with border. This results in bw validation failure. Signed-off-by:
Eric Yang <Eric.Yang2@amd.com> Reviewed-by:
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Yongqiang Sun authored
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Hersen Wu authored
Signed-off-by:
Hersen Wu <hersenxs.wu@amd.com> Signed-off-by:
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Tony Cheng authored
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Yongqiang Sun authored
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Charlene Liu authored
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Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Charlene Liu authored
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Ken Chalmers authored
Signed-off-by:
Ken Chalmers <ken.chalmers@amd.com> Reviewed-by:
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Yue Hin Lau authored
Signed-off-by:
Yue Hin Lau <Yuehin.Lau@amd.com> Reviewed-by:
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Yue Hin Lau authored
Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
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Eric Bernstein authored
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Eric Bernstein <eric.bernstein@amd.com> Reviewed-by:
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Eric Yang authored
A previous changed removed the hack to match mpcc_idd with mi instance. This causes pstate hang on resume from hibernate for yet unknown reason. Add the hack back for now to work around the issue. More debugging required in init_hw to root cause the hang. Signed-off-by:
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Wenjing Liu authored
[Description] hbr2 compliance eye output is unstable (toggling on and off) with debugger break. This caueses intermittent PHY automation failure. Need to look into the root cause later Signed-off-by:
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Yue Hin Lau authored
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Andrew Jiang authored
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ShihChen Chen authored
Signed-off-by:
ShihChen Chen <ShihChen.Chen@amd.com> Reviewed-by:
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Bhawanpreet Lakha authored
Split update_planes_and_stream_state (split Software and Hardware programming) as the state is already build, so we only need to program the hardware Signed-off-by:
Andrey Grodzovsky <Andrey.Grodzovsky@amd.com> Signed-off-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by:
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Jerry Zuo authored
Prevent NULL pointer on new_stream being added to ctx when added MST connectors cannot be found in existing crtc_state in the chained mode Signed-off-by:
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Jerry Zuo authored
Needs effort to take care of the fake sink scenario in downstream daisy chain device. Exclude MST from fake sink feature for now. Signed-off-by:
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Yue Hin Lau authored
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Leo (Sunpeng) Li authored
During system suspend, we: 1. Cache a duplicate of the current DRM atomic state, which calls hooks to duplicate our internal states. 2. Call hooks to disable all functionalities. 3. System suspended. During resume, we attempt to restore the cached state. However, our interal states are now stale, since step 1 was done before step 2. i.e. our cached state does not reflect the disabled nature of things. This change resolves that by destroying all relevant states to reflect the actual state during resume. Signed-off-by:
Leo (Sunpeng) Li <sunpeng.li@amd.com> Reviewed-by:
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Eric Bernstein authored
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Roman Li authored
- fixed wrong index in dce110_validate_surface_sets() - formatted for better readability Signed-off-by:
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Yue Hin Lau authored
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Harry Wentland authored
This was missed in the previous fake sink change. The fake sink allows us to enable a pipe with a disconnected display. We shouldn't report it as connected. Signed-off-by:
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Martin Tsai authored
Signed-off-by:
Martin Tsai <martin.tsai@amd.com> Reviewed-by:
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Roman Li authored
- Fixing text mode for cases when VT-switch doesn't result in timing change Signed-off-by:
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Eric Yang authored
A previous change moved link_disconnect_sink after dpcd read, this causes the sink count to be overwritten which in turn causes another detection to be triggered in the short pulse handler, which brings down the display. Signed-off-by:
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Andrew Jiang authored
This allows us to not always have scaling on, which causes issues with validation and causes the text to blur slightly. Signed-off-by:
Andrew Jiang <Andrew.Jiang@amd.com> Reviewed-by:
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Hersen Wu authored
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- 17 Oct, 2017 1 commit
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Martin Tsai authored
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