- 28 Sep, 2017 4 commits
-
-
vathsala nagaraju authored
Set frames before SU entry value for max resync frame count of dpcd register 2009, bit field 0:3. v2 : - add macro EDP_PSR2_FRAME_BEFORE_SU (Rodrigo) - remove EDP_FRAMES_BEFORE_SU_ENTRY (Rodrigo) - add check ==1 for dpcd_read call (ville) v3 : (Rodrigo) - move macro EDP_PSR2_FRAME_BEFORE_SU after EDP_PSR2_FRAME_BEFORE_SU - replace with &= v4 : - change the macro to shift value (jani) - updated register names Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> CC: Puthikorn Voravootivat <puthik@chromium.org> Reviewed-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
Vathsala Nagaraju <vathsala.nagaraju@intel.com> Signed-off-by:
-
vathsala nagaraju authored
Add defines for dpcd register 2009 (synchronization latency in sink). v2: - add spec version (Daniel) - use register name as is in spec,only drop excess from end (jani) - add the full register contents (jani) [Rodrigo fixed spec version when merging] Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> CC: Puthikorn Voravootivat <puthik@chromium.org> Reviewed-by:
-
Jani Nikula authored
Need MST sideband message transaction to power up/down nodes. Signed-off-by:Jani Nikula <jani.nikula@intel.com>
-
Tvrtko Ursulin authored
If we store the platform as a bitmask, and convert the IS_PLATFORM macro to use it, we allow the compiler to merge the IS_PLATFORM(a) || IS_PLATFORM(b) || ... checks into a single conditional. As a secondary benefit this saves almost 1k of text: text data bss dec hex filename -1460254 60014 3656 1523924 1740d4 drivers/gpu/drm/i915/i915.ko +1459260 60026 3656 1522942 173cfe drivers/gpu/drm/i915/i915.ko v2: Removed the infamous -1. Signed-off-by:Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Reviewed-by:
Chris Wilson <chris@chris-wilson.co.uk> Acked-by:
-
- 27 Sep, 2017 6 commits
-
-
git://people.freedesktop.org/~agd5f/linuxDave Airlie authored
First feature pull for 4.15. Highlights: - Per VM BO support - Lots of powerplay cleanups - Powerplay support for CI - pasid mgr for kfd - interrupt infrastructure for recoverable page faults - SR-IOV fixes - initial GPU reset for vega10 - prime mmap support - ttm page table debugging improvements - lots of bug fixes * 'drm-next-4.15' of git://people.freedesktop.org/~agd5f/linux: (232 commits) drm/amdgpu: clarify license in amdgpu_trace_points.c drm/amdgpu: Add gem_prime_mmap support drm/amd/powerplay: delete dead code in smumgr drm/amd/powerplay: delete SMUM_FIELD_MASK drm/amd/powerplay: delete SMUM_WAIT_INDIRECT_FIELD drm/amd/powerplay: delete SMUM_READ_FIELD drm/amd/powerplay: delete SMUM_SET_FIELD drm/amd/powerplay: delete SMUM_READ_VFPF_INDIRECT_FIELD drm/amd/powerplay: delete SMUM_WRITE_VFPF_INDIRECT_FIELD drm/amd/powerplay: delete SMUM_WRITE_FIELD drm/amd/powerplay: delete SMU_WRITE_INDIRECT_FIELD drm/amd/powerplay: move macros to hwmgr.h drm/amd/powerplay: move PHM_WAIT_VFPF_INDIRECT_FIELD to hwmgr.h drm/amd/powerplay: move SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL to hwmgr.h drm/amd/powerplay: move SMUM_WAIT_INDIRECT_FIELD_UNEQUAL to hwmgr.h drm/amd/powerplay: add new helper functions in hwmgr.h drm/amd/powerplay: use SMU_IND_INDEX/DATA_11 pair drm/amd/powerplay: refine powerplay code. drm/amd/powerplay: delete dead code in hwmgr.h drm/amd/powerplay: refine interface in struct pp_smumgr_func ...
-
git://anongit.freedesktop.org/git/drm-intelDave Airlie authored
Getting started with v4.15 features: - Cannonlake workarounds (Rodrigo, Oscar) - Infoframe refactoring and fixes to enable infoframes for DP (Ville) - VBT definition updates (Jani) - Sparse warning fixes (Ville, Chris) - Crtc state usage fixes and cleanups (Ville) - DP vswing, pre-emph and buffer translation refactoring and fixes (Rodrigo) - Prevent IPS from interfering with CRC capture (Ville, Marta) - Enable Mesa to advertise ARB_timer_query (Nanley) - Refactor GT number into intel_device_info (Lionel) - Avoid eDP DP AUX CH timeouts harder (Manasi) - CDCLK check improvements (Ville) - Restore GPU clock boost on missed pageflip vblanks (Chris) - Fence register reservation API for vGPU (Changbin) - First batch of CCS fixes (Ville) - Finally, numerous GEM fixes, cleanups and improvements (Chris) * tag 'drm-intel-next-2017-09-07' of git://anongit.freedesktop.org/git/drm-intel: (100 commits) drm/i915: Update DRIVER_DATE to 20170907 drm/i915/cnl: WaThrottleEUPerfToAvoidTDBackPressure:cnl(pre-prod) drm/i915: Lift has-pinned-pages assert to caller of ____i915_gem_object_get_pages drm/i915: Display WA #1133 WaFbcSkipSegments:cnl, glk drm/i915/cnl: Allow the reg_read ioctl to read the RCS TIMESTAMP register drm/i915: Move device_info.has_snoop into the static tables drm/i915: Disable MI_STORE_DATA_IMM for i915g/i915gm drm/i915: Re-enable GTT following a device reset drm/i915/cnp: Wa 1181: Fix Backlight issue drm/i915: Annotate user relocs with __user drm/i915: Constify load detect mode drm/i915/perf: Remove __user from u64 in drm_i915_perf_oa_config drm/i915: Silence sparse by using gfp_t drm/i915: io unmap functions want __iomem drm/i915: Add __rcu to radix tree slot pointer drm/i915: Wake up the device for the fbdev setup drm/i915: Add interface to reserve fence registers for vGPU drm/i915: Use correct path to trace include drm/i915: Fix the missing PPAT cache attributes on CNL drm/i915: Fix enum pipe vs. enum transcoder for the PCH transcoder ...
-
git://anongit.freedesktop.org/git/drm-miscDave Airlie authored
UAPI Changes: Cross-subsystem Changes: Core Changes: - DP SDP defines (Ville) - polish for scdc helpers (Thierry Reding) - fix lifetimes for connector/plane state across crtc changes (Maarten Lankhorst). - sparse fixes (Ville+Thierry) - make legacy kms ioctls all interruptible (Maarten) - push edid override into the edid helpers (out of probe helpers) (Jani) - DP ESI defines for link status (DK) Driver Changes: - drm-panel is now in drm-misc! - minor panel-simple cleanups/refactoring by various folks - drm_bridge_add cleanup (Inki Dae) - constify a few i2c_device_id structs (Arvind Yadav) - More patches from Noralf's fb/gem helper cleanup - bridge/synopsis: reset fix (Philippe Cornu) - fix tracepoint include handling in drivers (Thierry) - rockchip: lvds support (Sandy Huang) - move sun4i into drm-misc fold (Maxime Ripard) - sun4i: refactor driver load + support TCON backend/layer muxing (Chen-Yu Tsai) - pl111: support more pl11x variants (Linus Walleij) - bridge/adv7511: robustify probing/edid handling (Lars-Petersen Clausen) New hw support: - S6E63J0X03 panel (Hoegeun Kwon) - OTM8009A panel (Philippe CORNU) - Seiko 43WVF1G panel (Marco Franchi) - tve200 driver (Linus Walleij) Plus assorted of tiny patches all over, including our first outreachy patches from applicants for the winter round! * tag 'drm-misc-next-2017-09-20' of git://anongit.freedesktop.org/git/drm-misc: (101 commits) drm: add backwards compatibility support for drm_kms_helper.edid_firmware drm: handle override and firmware EDID at drm_do_get_edid() level drm/dp: DPCD register defines for link status within ESI field drm/rockchip: Replace dev_* with DRM_DEV_* drm/tinydrm: Drop driver registered message drm/gem-fb-helper: Use debug message on gem lookup failure drm/imx: Use drm_gem_fb_create() and drm_gem_fb_prepare_fb() drm/bridge: adv7511: Constify HDMI CODEC platform data drm/bridge: adv7511: Enable connector polling when no interrupt is specified drm/bridge: adv7511: Remove private copy of the EDID drm/bridge: adv7511: Properly update EDID when no EDID was found drm/crtc: Convert setcrtc ioctl locking to interruptible. drm/atomic: Convert pageflip ioctl locking to interruptible. drm/legacy: Convert setplane ioctl locking to interruptible. drm/legacy: Convert cursor ioctl locking to interruptible. drm/atomic: Convert atomic ioctl locking to interruptible. drm/atomic: Prepare drm_modeset_lock infrastructure for interruptible waiting, v2. drm/tve200: Clean up panel bridging drm/doc: Update todo.rst drm/dp/mst: Sideband message transaction to power up/down nodes ...
-
Rodrigo Vivi authored
Let's stop this usage before it spreads so much. 1. This check is not part of usual searches happening when adding new platform. 2. There is already a duplication here with INTEL_INFO(dev_priv)->gen and INTEL_GEN(dev_priv). So let's please avoid yet another way. Cc: Lyude <cpaul@redhat.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Daniel Vetter <daniel.vetter@intel.com> Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Shashank Sharma <shashank.sharma@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by:
Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by:
Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170926211346.12009-1-rodrigo.vivi@intel.com
-
Helge Deller authored
Use the %pS printk format for printing symbols from direct addresses. This is important for the ia64, ppc64 and parisc64 architectures, while on other architectures there is no difference between %pS and %pF. Fix it for consistency across the kernel. Signed-off-by:
Helge Deller <deller@gmx.de> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: David Airlie <airlied@linux.ie> Cc: intel-gfx@lists.freedesktop.org Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/1504729681-3504-6-git-send-email-deller@gmx.de
-
Chris Wilson authored
When cancelling requests, also send the notification to any listeners (gvt) that the request is no longer scheduled on hw. They may require to keep the in/out exactly balanced, and so the reuse after the reset may confuse the listener. Fixes: 221ab971 ("drm/i915/execlists: Unwind incomplete requests on resets") Signed-off-by:
Mika Kuoppala <mika.kuoppala@linux.intel.com>
-
- 26 Sep, 2017 30 commits
-
-
Ben Widawsky authored
Cannonlake Slice and Subslice information has changed. This patch initially provided by Ben adds the proper sseu initialization. v2: This v2 done by Rodrigo includes: - Fix on Total slices count by avoiding [1][2] and [2][2]. - Inclusion of EU Per Subslice. - Commit message. v3: This v3 done by Rodrigo includes: - Handle all possible bits and extra fuse register. - Use INTEL_GEN macro. - Fully assume uniform distribution so remove union with eu_per_subslice and add proper the comment. v4: This v4 done by Rodrigo includes: - Consider all bits available: 6 bits for slices [27:22] and 4 for subslices [21:18]. v5: This v5 done by Rodrigo includes: - sseu->subslice_mask = (1 << 4) - 1 - missed on previous versions and noticed by Oscar. Cc: Oscar Mateo <oscar.mateo@intel.com> Signed-off-by:Ben Widawsky <ben@bwidawsk.net> Signed-off-by:
Oscar Mateo <oscar.mateo@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170920183525.20530-1-rodrigo.vivi@intel.com
-
Alex Deucher authored
It was not clear. The rest of the driver is MIT/X11. Reviewed-by:
Christian König <christian.koenig@amd.com> Acked-by:
Dave Airlie <airlied@redhat.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
-
Samuel Li authored
v2: drop hdp invalidate/flush. v3: honor pgoff during prime mmap. Add a barrier after cpu access. v4: drop begin/end_cpu_access() for now, revisit later. Signed-off-by:
Samuel Li <Samuel.Li@amd.com> Reviewed-by:
-
Rex Zhu authored
Reviewed-by:
Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
-
Rex Zhu authored
repeated defining in hwmgr.h Reviewed-by:
-
Rex Zhu authored
repeated defining in hwmgr.h use PHM_WAIT_INDIRECT_FIELD instand. Reviewed-by:
-
Rex Zhu authored
repeated defining in hwmgr.h Reviewed-by:
-
Rex Zhu authored
repeated defining in hwmgr.h Reviewed-by:
-
Rex Zhu authored
repeated defining in hwmgr.h Reviewed-by:
-
Rex Zhu authored
repeated defining in hwmgr.h Reviewed-by:
-
Rex Zhu authored
the macro is as same as PHM_WRITE_FIELD Reviewed-by:
-
Rex Zhu authored
the macro is as same as PHM_WRITE_INDIRECT_FIELD Reviewed-by:
-
Rex Zhu authored
the macro is not relevant to SMU, so rename SMU_WAIT_FIELD_UNEQUAL to PHM_WAIT_FIELD_UNEQUAL and move to hwmgr.h Reviewed-by:
-
Rex Zhu authored
the macro is not relevant to SMU, so move to hwmgr.h and rename to PHM_WAIT_VFPF_INDIRECT_FIELD Reviewed-by:
-
Rex Zhu authored
the macro is not relevant to SMU, so move to hwmgr.h and rename to PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL Reviewed-by:
-
Rex Zhu authored
the macro is not relevent to SMU, so move to hwmgr.h and rename to PHM_WAIT_INDIRECT_FIELD_UNEQUAL Reviewed-by:
-
Rex Zhu authored
Reviewed-by:
-
Rex Zhu authored
in VFPF macros to support virtualization Reviewed-by:
-
Rex Zhu authored
delete struct smumgr, put smu backend function table in struct hwmgr Reviewed-by:
-
Rex Zhu authored
Reviewed-by:
-
Rex Zhu authored
unify to use struct hwmgr as function parameter in smumgr. Reviewed-by:
-
Christian König authored
Just set the CPU access required flag when we pin it. Signed-off-by:
-
Monk Liu authored
this fix memory leak due to request_firmware after driver unloaded v2: release gmc firmware for gmc6/7/8 as well Signed-off-by:
Monk Liu <Monk.Liu@amd.com> Reviewed-by:
-
Monk Liu authored
fix missing finish uvd enc_ring. v2: since the adev pointer check in already in ring_fini so drop the check outsider Signed-off-by:
-
Monk Liu authored
this way after KIQ MQD released in drv unloading, CPC can still let KIQ access this MQD thus RLCV SAVE_VF will not fail v2: always use VRAM domain for KIQ MQD no matter BM or SRIOV Signed-off-by:
-
Monk Liu authored
v2: move kcq_disable out of SRIOV, make it genearal Signed-off-by:
-
Monk Liu authored
only with this way we can debug the VMC page fault issue Signed-off-by:
-
Yong Zhao authored
Use it to replace the hard coded value in amdgpu_vm_bo_update_mapping(). Signed-off-by:
Yong Zhao <yong.zhao@amd.com> Reviewed-by:
-
Yong Zhao authored
When max_bytes is not 8 bytes aligned and bo size is larger than max_bytes, the last 8 bytes in a ttm node may be left unchanged. For example, on pre SDMA 4.0, max_bytes = 0x1fffff, and the bo size is 0x200000, the problem will happen. In order to fix the problem, we separately store the max nums of PTEs/PDEs a single operation can set in amdgpu_vm_pte_funcs structure, rather than inferring it from bytes limit of SDMA constant fill, i.e. fill_max_bytes. Together with the fix, we replace the hard code value "10" in amdgpu_vm_bo_update_mapping() with the corresponding values from structure amdgpu_vm_pte_funcs. Signed-off-by:
-
Yong Zhao authored
Signed-off-by:
-
