- 20 May, 2013 1 commit
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braggle@free.fr authored
This patch add dvo detection for the Chrontel 7010B on some old hardware. References: https://bugzilla.kernel.org/show_bug.cgi?id=55101 Signed-off-by: Braggle <braggle at free.fr> [danvet: Fix up whitespace mangling.] Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch>
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- 14 May, 2013 3 commits
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Daniel Vetter authored
Allows us to rip out a few fragile checks (which are duplicated in the hw state readout now, too). Also prepares us a bit for more than one panel/pfit. Reviewed-by:
Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by:
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Daniel Vetter authored
No more need to guard the write with a power well check on Haswell now that we have proper pfit state readout: We can simply only clear the pfit if it's actually on. This removes some duplication of knowledge between the haswell pfit disable and pfit state readout code about. While at it extract a little helper for this. Reviewed-by:
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Daniel Vetter authored
Pfit state readout is a bit ugly on gen2/3 due to the intermingling with the lvds state, but alas. Also note that since state is always cleared to zero we can unconditonally compare all the state and completely neglect the actual platform we're running on. v2: Properly check for the pfit power domain on haswell. v3: Don't check pgm_ratios on gen4+, they're auto-computed by the hw. v4: Properly clear the lvds border bits, upset the state checker a bit. v5: Unconditionally read out panel dither settings on gen2/3. Reviewed-by:
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- 10 May, 2013 36 commits
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Paulo Zanoni authored
This should prevent mode set failures on LPT. Signed-off-by:
Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by:
Damien Lespiau <damien.lespiau@intel.com> [danvet: Pimp the w/a tag to fit into Damien's new scheme.] Signed-off-by:
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Damien Lespiau authored
There was a race between Rodrigo writing those patches and me formalizing the addition of platform tags. This patches fixes it. Signed-off-by:
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Daniel Vetter authored
Somehow this has been forgotten in commit 1974cad0 Author: Daniel Vetter <daniel.vetter@ffwll.ch> Date: Mon Nov 26 17:22:09 2012 +0100 drm/i915: move is_dual_link_lvds to intel_lvds.c Reviewed-by:
Jani Nikula <jani.nikula@intel.com> Signed-off-by:
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Damien Lespiau authored
Up to now, we were using a static table to match the clock frequency with a (r2,n2,p) triplet. Despite this table being big, it's by no mean comprehensive and we had to fall back to the closest frequency when the requested TMDS clock wasn't in the table. This patch computes (r2,n2,p) dynamically and get rid of The Big Table. v2: Replace the floating point constant 1e6 by 1000000 Bugzilla: http://bugs.freedesktop.org/show_bug.cgi?id=58497Signed-off-by:
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Rodrigo Vivi authored
Display register 46500h bit 23 must be set to 1b for the entire time that Frame Buffer Compression is enabled. v2: Ville suggested to enable it back when disabling fbc to avoid wasting power. v3: RMW to preserve other bits (by Ville) v4: Fix from Ville: sed &/| at RMW v5: Too far on sed. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
Rodrigo Vivi <rodrigo.vivi@gmail.com> [danvet: Insert missing space that checkpatch spotted.] Signed-off-by:
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Rodrigo Vivi authored
Display register 420B0h bit 22 must be set to 1b for the entire time that Frame Buffer Compression is enabled. Reviewed-by:
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Rodrigo Vivi authored
This patch introduce Frame Buffer Compression (FBC) support for HSW. FBC is tied to primary plane A in HSW. v2: Ville pointed out docs say FBC must be disabled before disabling the plane on HSW. v3: Really enabling it by default at HSW. Reviewed-by: -
Rodrigo Vivi authored
Display register 42020h bit 9 must be set to 1b for the entire time that Frame Buffer Compression is enabled. v2: RMW to preserve other bits (by Ville) v3: Fix from Ville: sed &/| at RMW v4: Too far on sed. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
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Rodrigo Vivi authored
Display register 42000h bit 22 must be set to 1b for the entire time that Frame Buffer Compression is enabled. Reviewed-by:
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Rodrigo Vivi authored
This patch introduce Frame Buffer Compression (FBC) support for IVB, without enabling it by default. It adds a new function gen7_enable_fbc to avoid getting ironlake_enable_fbc messed with many IS_IVYBRIDGE checks. v2: Fixes from Ville. * Fix Plane. FBC is tied to primary plane A in HSW * Fix DPFC initial write to avoid let trash on the register. v3: Checking for bad plane on intel_update_fbc() as Chris suggested. v4: Ville pointed out that according to BSpec FBC_CTL bits 0:3 must be 0. v5: Up to v4 this work was entirely focused on Haswell. However Ville noticed I could reuse the FBC work done for HSW and get FBC for free at Ivybridge. So it makes more sense enable FBC for IVB first. FBC for HSW comming on next patches. We are just not enabling it by default on IVB. v6: Fix confused commit name (by Matt Turner). v7: Remove gtt_offset shift since it is page aligned byte offset (by Ville). Cc: Matt Turner <mattst88@gmail.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: -
Rodrigo Vivi authored
drm_i915_private is getting bigger and bigger when adding new vbt stuff. So, the better way of getting drm_i915_private organized is to create a special structure for vbt stuff. v2: Basically conflicts fixes Reviewed-by:
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Daniel Vetter authored
We need to track this correctly. While at it shovel the boolean to track whether the sdvo is in tv mode or not into pipe_config. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=36997Tested-by:
Pierre Assal <pierre.assal@verint.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=63609Tested-by:
cancan,feng <cancan.feng@intel.com> Reviewed-by:
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Daniel Vetter authored
More ugly stuff gone for good! The big special case left now is lvds (which is indeed really special). Reviewed-by:
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Daniel Vetter authored
This seems to be an impressive piece of copy&pasta lore. I've checked all docs and on most platforms these bits are all MBZ, with the exception of the SDVO pixel multiplier on gen3. On gen4 that moved to a special DPLL_MD registers. No indication whatsoever that we actually need this for native TV-out support. I suspect this started as a hack when we didn't yet have proper pixel multiplier support in place for SDVO TV, but then got stuck in a life of its own. Just rip it out. Reviewed-by:
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Daniel Vetter authored
TV-out uses the same reference clock as everyone else. The only difference seems to be in the slightly different CB tuning limit. Note that PLL_REF_INPUT_TVCLKINBC is a reserved value on ilk+. Also strictly speaking we don't support native TV-out on ilk+, hence all that code is dead. But Bspec still contains some residual mentions of native TV-out on some pch-split platforms, so I've figured it doesn't hurt to keep the code around a bit longer (e.g. in the cb tune function). v2: Improve the commit message as Jani suggested in his review. Reviewed-by:
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Daniel Vetter authored
We have a very nice infrastructure for this now! Note that the multifunction sdvo support is pretty neatly broken: We completely ignore userspace's request for which connector to wire up with the encoder and just use whatever the last detect callback has seen. Not something I'll fix in this patch, but unfortunately something which is also broken in the DDI code ... v2: Don't call sdvo_tv_clock twice. Reviewed-by:
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Imre Deak authored
Signed-off-by:
Imre Deak <imre.deak@intel.com> Signed-off-by:
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Imre Deak authored
There are no more users for these, so remove them. Signed-off-by:
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Imre Deak authored
is_pch_edp() will be removed by the next patch, so replace it by a check for the port and device type. Signed-off-by:
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Imre Deak authored
is_pch_edp() will be removed in a follow-up patch, so replace it with a check for the port and VBT info (for port-D eDP). Also make things a bit clearer by using a switch on the ports. v2: - make the comment about not setting the conder type for DP clearer (Ville) Signed-off-by:
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Imre Deak authored
On ILK-IVB the CPU side eDP is always on port-A. Also reduce somewhat the debug verbosity. v2: - reduce debug verbosity Signed-off-by:
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Imre Deak authored
On HSW the CPU side eDP is always on port-A, the PCH side eDP is always on port-D. Signed-off-by:
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Imre Deak authored
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Jesse Barnes authored
Works pretty well actually. Signed-off-by:
Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by:
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Jesse Barnes authored
In some cases, we may not need GTT address space allocated to a stolen object, so allow passing -1 to the preallocated function to indicate as much. v2: remove BUG_ON(gtt_offset & 4095) now that -1 is allowed (Ville) Reviewed-by:
Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
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Jesse Barnes authored
But we need to get the right stolen base and make pre-allocated objects for BIOS stuff so we don't clobber it. If the BIOS hasn't allocated a power context, we allocate one here too, from stolen space as required by the docs. v2: fix stolen to phys if ladder (Ben) keep BIOS reserved space out of allocator altogether (Ben) v3: fix mask of stolen base (Ben) v4: clean up preallocated object on unload (Ben) don't zero reg on unload (Jesse) fix mask harder (Jesse) v5: use unref for freeing stolen bits (Chris) move alloc/free to intel_pm.c (Chris) v6: NULL pctx at disable time so error paths work (Ben) v7: use correct PCI device for config read (Jesse) Reviewed-by:Ben Widawsky <benjamin.widawsky@intel.com> Signed-off-by:
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Ville Syrjälä authored
If the calculated FBC watermark is no good, we simply disable FBC watermarks. But we fail to re-enable them later if the calculated watermark becomes good again. Fix that, but remember to leave FBC watermarks disabled on ILK since that's required by some workarounds. v2: Fix checkpatch complaint Signed-off-by:
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Imre Deak authored
For the device to enter D3 we should enable PCH clock gating. v2: - use HAS_PCH_LPT instead of IS_HASWELL (Ville, Paolo) - rename lpt_allow_clock_gating to lpt_suspend_hw (Paolo) Signed-off-by:
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Jani Nikula authored
commit 142e2398 Author: Egbert Eich <eich@suse.de> Date: Thu Apr 11 15:57:57 2013 +0200 drm/i915: Add bit field to record which pins have received HPD events (v3) added a bit field for hotplug event tracking. There ended up being three different v3 of the patch: [1], [2], and [3]. Apparently [1] was the correct one, but some frankenstein combination of the three got committed, which reversed the logic for setting the hotplug bits and misplaced a continue statement, skipping the hotplug irq storm handling altogether. This lead to broken hotplug detection, bisected to commit 321a1b30 Author: Egbert Eich <eich@suse.de> Date: Thu Apr 11 16:00:26 2013 +0200 drm/i915: Only reprobe display on encoder which has received an HPD event (v2) which uses the incorrectly set hotplug event bits. Fix the mess. [1] http://mid.gmane.org/1366112220-7638-6-git-send-email-eich@suse.de [2] http://mid.gmane.org/1365688677-13682-1-git-send-email-eich@suse.de [3] http://mid.gmane.org/1365688996-13874-1-git-send-email-eich@suse.deSigned-off-by:
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Damien Lespiau authored
We did not mention the workaround name when implementing those. This should help us track what we already implement. Signed-off-by:
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Damien Lespiau authored
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Paulo Zanoni authored
We already have the same check on intel_enable_ddi. This patch prevents "unclaimed register" messages when the power well is disabled. V2: Reset intel_crtc->eld_vld to false after the mode_set function. V3: Add both "type != INTEL_OUTPUT_EDP" requested. Signed-off-by:
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Paulo Zanoni authored
This fixes "unclaimed register" messages when the power well is disabled and there's a GPU hang. v2: Use the new intel_display_power_enabled(). v3: Use the new domains for intel_display_power_enabled(). Signed-off-by:
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Paulo Zanoni authored
In the error state function we read the registers without checking if the power well is on, so after doing this we have to clear the FPGA_DBG_RM_NOCLAIM bit to prevent the next I915_WRITE from detecting it and printing an error message. The first version of this patch was checking for the power well state and then avoiding reading registers that were off, but the reviewers requested to just read the registers any way and then later clear the FPGA_DBG_RM_NOCLAIM bit. Signed-off-by:
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Paulo Zanoni authored
We need to dump these registers if we want to properly interpret the others. Signed-off-by:
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Paulo Zanoni authored
This should replace intel_using_power_well. The idea is that we're adding the requested power domain as an argument, so this might enable the code to look less platform-specific and also allows us to easily add new domains in case we need. v2: Add more domains to enum intel_display_power_domain v3: Even more domains requested Requested-by:
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