1. 16 Jul, 2016 21 commits
    • Archit Taneja's avatar
      drm/msm/mdp5: Add MDSS top level driver · 990a4007
      Archit Taneja authored
      SoCs that contain MDP5 have a top level wrapper called MDSS that manages
      clocks, power and irq for the sub-blocks within it.
      
      Currently, the MDSS portions are stuffed into the MDP5 driver. This makes
      it hard to represent the DT bindings in the correct way. We create a top
      level MDSS helper that handles these parts. This is essentially moving out
      some of the mdp5_kms irq code and MDSS register space and keeping it as a
      separate entity. We haven't given any clocks to the top level MDSS yet,
      but a AHB clock would be added in the future to access registers.
      
      One thing to note is that the resources allocated by this helper are
      tied to the top level platform_device (the one that allocates the
      drm_device struct too). This device would be the parent to MDSS
      sub-blocks like MDP5, DSI, eDP etc.
      Signed-off-by: default avatarArchit Taneja <architt@codeaurora.org>
      Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
      990a4007
    • Archit Taneja's avatar
      drm/msm: Get irq number within kms driver itself · a2b3a557
      Archit Taneja authored
      The driver gets the irq number using platform_get_irq on the main kms
      platform device. This works fine since both MDP4 and MDP5 currently
      have a flat device hierarchy. The platform device tied with the
      drm_device points to the MDP DT node in both cases.
      
      This won't work when MDP5 supports a tree-like hierarchy. In this
      case, the platform device tied to the top level drm_device is the
      MDSS DT node, and the irq we need for KMS is the one generated by
      MDP5, not MDSS.
      
      Get the irq number from the MDP4/5 kms driver itself. Each driver
      can later provide the irq number based on what device hierarchy it
      uses.
      
      While we're at it, call drm_irq_install only when we have a valid KMS
      driver.
      Signed-off-by: default avatarArchit Taneja <architt@codeaurora.org>
      Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
      a2b3a557
    • Archit Taneja's avatar
      drm/msm: Remove unused fields · 7429d860
      Archit Taneja authored
      These aren't used. Probably left overs when driver was refactored to
      support both MDP4 and MDP5.
      Signed-off-by: default avatarArchit Taneja <architt@codeaurora.org>
      Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
      7429d860
    • Archit Taneja's avatar
      drm/msm: Drop the id_table in platform_driver · 6a5625d8
      Archit Taneja authored
      This isn't needed as we only support OF.
      Signed-off-by: default avatarArchit Taneja <architt@codeaurora.org>
      Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
      6a5625d8
    • Archit Taneja's avatar
      dt-bindings: msm/dsi: Some binding doc cleanups · a3c463e0
      Archit Taneja authored
      Some cleanups:
      
      - Use simpler names for DT nodes in the example
      - Use references instead of dumping Document links everywhere
      Acked-by: default avatarRob Herring <robh@kernel.org>
      Signed-off-by: default avatarArchit Taneja <architt@codeaurora.org>
      Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
      a3c463e0
    • Archit Taneja's avatar
      dt-bindings: msm/dsi: Add assigned clocks bindings · 9097209d
      Archit Taneja authored
      The PLL in the DSI PHY block generates 2 clock outputs (Byte and Pixel
      clocks) that are fed into the Multimedia Clock Controller (MMCC). The MMCC
      uses these as source clocks for some of its RCGs to generate clocks that
      finally feed to the DSI host controller.
      
      Use the assigned clocks DT bindings to set up the MMCC RCGs that feed to
      the DSI host. Use the DSI PHY provided clocks to set up the parents
      of these assigned clocks.
      Acked-by: default avatarRob Herring <robh@kernel.org>
      Signed-off-by: default avatarArchit Taneja <architt@codeaurora.org>
      Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
      9097209d
    • Archit Taneja's avatar
      dt-bindings: msm/dsi: Modify port and PHY bindings · 8042b778
      Archit Taneja authored
      The DSI node now has two ports that describe the connection between the
      MDP interface output and the DSI input, and the connection between the DSI
      output and the connected panel/bridge. Update the properties and the
      example.
      
      Also, use generic PHY bindings instead of the custom one.
      Acked-by: default avatarRob Herring <robh@kernel.org>
      Signed-off-by: default avatarArchit Taneja <architt@codeaurora.org>
      Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
      8042b778
    • Archit Taneja's avatar
      dt-bindings: msm/dsi: Use standard data lanes binding · cb9b08e9
      Archit Taneja authored
      The "qcom,data-lane-map" binding mentioned in the document is changed to
      the more generic "data-lanes" property specified in:
      
      Documentation/devicetree/bindings/media/video-interfaces.txt
      
      The previous binding expressed physical to logical data lane mappings,
      the standard "data-lanes" binding uses logical to physical data lane
      mappings. Update the docs to reflect this change. The example had the
      property incorrectly named as "lanes", update this too.
      
      The MSM DSI DT bindings aren't used anywhere at the moment, so
      it's okay to update this property.
      Acked-by: default avatarRob Herring <robh@kernel.org>
      Signed-off-by: default avatarArchit Taneja <architt@codeaurora.org>
      Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
      cb9b08e9
    • Archit Taneja's avatar
      drm/msm/dsi: Use a standard DT binding for data lanes · 60282cea
      Archit Taneja authored
      A more standard DT binding describing data lanes already exists here:
      Documentation/devicetree/bindings/media/video-interfaces.txt
      
      Use this binding instead of "qcom,data-lane-map". One difference
      in the standard binding w.r.t to the existing binding is that it
      provides a logical to physical mapping instead of the other way
      round. Tweak the code to translate the data the way we want it.
      
      The MSM DSI DT bindings aren't used anywhere at the moment, so
      it's okay to update this property.
      Signed-off-by: default avatarArchit Taneja <architt@codeaurora.org>
      Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
      60282cea
    • Archit Taneja's avatar
      drm/msm/dsi: Use generic PHY bindings · 69696ea0
      Archit Taneja authored
      The DSI host links to the DSI PHY device using a custom binding. Switch to
      the generic PHY bindings. The DSI PHY driver itself doesn't use the common
      PHY framework for now.
      Signed-off-by: default avatarArchit Taneja <architt@codeaurora.org>
      Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
      69696ea0
    • Archit Taneja's avatar
      drm/msm/dsi: Modify port parsing · b9ac76f6
      Archit Taneja authored
      The DSI interface is going to have two ports defined in its device node.
      The first port is always going to be the link between the MDP output
      and the input to DSI, the second port is going to be the link between
      the DSI output and the connected panel/bridge:
      
       -----           -----           -------
      | MDP | ------> | DSI | ------> | Panel |
       -----           -----           -------
              (Port 0)       (Port 1)
      
      Until now, there was only one Port representing the output. Update the
      DSI host driver such that it parses Port #1 for a connected device.
      Signed-off-by: default avatarArchit Taneja <architt@codeaurora.org>
      Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
      b9ac76f6
    • Archit Taneja's avatar
      dt-bindings: msm/mdp: Fix up clock related bindings · 1f238536
      Archit Taneja authored
      Address some issues wiht clock related bindings. It's okay to change these
      since these bindings aren't used in any dtsi files until now.
      
      MDP5:
      - Don't ask for source clock
      
      MDP4:
      - Give a better name for MDP_TV_CLK
      - Remove TV_SRC
      - Add MDP_AXI_CLK
      Acked-by: default avatarRob Herring <robh@kernel.org>
      Signed-off-by: default avatarArchit Taneja <architt@codeaurora.org>
      Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
      1f238536
    • Archit Taneja's avatar
      drm/msm/mdp4: Clean up some MDP4 clocks · db9e44fb
      Archit Taneja authored
      Fix some issues with MDP4 clocks:
      
      - mdp4_dtv_encoder tries to get "src_clk", which is a RCG(TV_SRC) in
        MSM8960 and APQ8064. This isn't something the driver should access or
        configure. Instead of this, configure the "mdp_clk" (MDP_TV_CLK), a
        branch clock in MMCC that has the TV_SRC as its parent. Setting
        rate/enabling the "mdp_clk" will eventually configure "src_clk", which
        is what we want.
      - Rename "mdp_clk" to "tv_clk" because that's slightly less confusing.
      - Rename "mdp_axi_clk" to "bus_clk" because that's what we do elsewhere
        too.
      Signed-off-by: default avatarArchit Taneja <architt@codeaurora.org>
      Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
      db9e44fb
    • Archit Taneja's avatar
      drm/msm/mdp5: Don't get source of MDP core clock · 0e0d9dfe
      Archit Taneja authored
      The driver expects DT to provide the parent to MDP core clock. The only
      operation done to the parent clock is to set a rate. This can be
      achieved by setting the rate on the core clock itsef. Don't try to
      get the parent clock anymore.
      Signed-off-by: default avatarArchit Taneja <architt@codeaurora.org>
      Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
      0e0d9dfe
    • Archit Taneja's avatar
      drm/msm: Print the correct virtual addresses in map/unmap funcs · cbe4295a
      Archit Taneja authored
      The msm_iommu_map/unmap funcs have debug prints to show the list of
      VA:PA mappings. Use the correct variable to print the VAs.
      Signed-off-by: default avatarArchit Taneja <architt@codeaurora.org>
      Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
      cbe4295a
    • Archit Taneja's avatar
      drm/msm: Use correct type for physical addresses · 69be1f4e
      Archit Taneja authored
      The u32 type used to pass the physical addresses to iommu_map can't
      accommodate 64 bit addresses. Move to dma_addr_t to ensure wrong
      addresses aren't provided to the IOMMU driver.
      Signed-off-by: default avatarArchit Taneja <architt@codeaurora.org>
      Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
      69be1f4e
    • Dave Airlie's avatar
      Merge tag 'drm-vc4-next-2016-07-15' of https://github.com/anholt/linux into drm-next · 2d635fde
      Dave Airlie authored
      This pull request brings in vc4 shader validation for branching,
      allowing GLSL shaders with non-unrolled loops.
      
      * tag 'drm-vc4-next-2016-07-15' of https://github.com/anholt/linux:
        drm/vc4: Fix a "the the" typo in a comment.
        drm/vc4: Fix definition of QPU_R_MS_REV_FLAGS
        drm/vc4: Add a getparam to signal support for branches.
        drm/vc4: Add support for branching in shader validation.
        drm/vc4: Add a bitmap of branch targets during shader validation.
        drm/vc4: Move validation's current/max ip into the validation struct.
        drm/vc4: Add a getparam ioctl for getting the V3D identity regs.
      2d635fde
    • Dave Airlie's avatar
      Merge tag 'drm/panel/for-4.8-rc1' of git://anongit.freedesktop.org/tegra/linux into drm-next · ec2174fe
      Dave Airlie authored
      drm/panel: Changes for v4.8-rc1
      
      This set of changes contains a few cleanups for existing panels as well
      as improved handling of certain backlights. In addition there's support
      for a few new simple panels.
      
      * tag 'drm/panel/for-4.8-rc1' of git://anongit.freedesktop.org/tegra/linux:
        drm/panel: simple: Add support for Starry KR122EA0SRA panel
        dt-bindings: Add Starry KR122EA0SRA panel binding
        dt-bindings: Add vendor prefix for Starry
        dt-bindings: display: Add Sharp LQ101K1LY04 panel binding
        drm/panel: simple: Add support for Sharp LQ101K1LY04
        drm/panel: simple: Add support for LG LP079QX1-SP0V panel
        dt-bindings: Add support for LG LP079QX1-SP0V panel
        drm/panel: simple: Add support for Sharp LQ123P1JX31 panel
        dt-bindings: Add Sharp LQ123P1JX31 panel binding
        drm/panel: simple: Add support for Samsung LSN122DL01-C01 panel
        dt-bindings: Add Samsung LSN122DL01-C01 panel binding
        drm/panel: simple: Add support for LG LP097QX1-SPA1 panel
        dt-bindings: Add LG LP097QX1-SPA1 panel binding
        drm/panel: simple: Update backlight state property
        drm/panel: simple: Remove gratuitous blank line
        drm/panel: simple: Fix a couple of physical sizes
      ec2174fe
    • Dave Airlie's avatar
      Merge tag 'drm/tegra/for-4.8-rc1' of git://anongit.freedesktop.org/tegra/linux into drm-next · 877fa9a4
      Dave Airlie authored
      drm/tegra: Changes for v4.8-rc1
      
      This set of changes contains a bunch of cleanups to the host1x driver as
      well as the addition of a pin controller for DPAUX, which is required by
      boards to configure the DPAUX pads in AUX mode (for DisplayPort) or I2C
      mode (for HDMI and DDC).
      
      Included is also a bit of rework of the SOR driver in preparation to add
      DisplayPort support as well as some refactoring and cleanup.
      
      Finally, all output drivers are converted to runtime PM, which greatly
      simplifies the handling of clocks and resets.
      
      * tag 'drm/tegra/for-4.8-rc1' of git://anongit.freedesktop.org/tegra/linux: (35 commits)
        drm/tegra: sor: Reject HDMI 2.0 modes
        drm/tegra: sor: Prepare for generic PM domain support
        drm/tegra: dsi: Prepare for generic PM domain support
        drm/tegra: sor: Make XBAR configurable per SoC
        drm/tegra: sor: Use sor1_src clock to set parent for HDMI
        dt-bindings: display: tegra: Add source clock for SOR
        drm/tegra: sor: Implement sor1_brick clock
        drm/tegra: sor: Implement runtime PM
        drm/tegra: hdmi: Implement runtime PM
        drm/tegra: dsi: Implement runtime PM
        drm/tegra: dc: Implement runtime PM
        drm/tegra: hdmi: Enable audio over HDMI
        drm/tegra: sor: Do not support deep color modes
        drm/tegra: sor: Extract tegra_sor_mode_set()
        drm/tegra: sor: Split out tegra_sor_apply_config()
        drm/tegra: sor: Rename tegra_sor_calc_config()
        drm/tegra: sor: Factor out tegra_sor_set_parent_clock()
        drm/tegra: dpaux: Add pinctrl support
        dt-bindings: Add bindings for Tegra DPAUX pinctrl driver
        drm/tegra: Prepare DPAUX for supporting generic PM domains
        ...
      877fa9a4
    • Dave Airlie's avatar
      Merge branch 'upstream/analogix-dp-20160705' of git://github.com/yakir-Yang/linux into drm-next · e2b80bac
      Dave Airlie authored
      Please consider merging this tag, which contains the v4 misc fixes and add RK3399 eDP support patches[0] I sent on 2016-06-29, rebased onto v4.7-rc5.
      
      * 'upstream/analogix-dp-20160705' of git://github.com/yakir-Yang/linux:
        dt-bindings: analogix_dp: rockchip: correct the wrong compatible name
        drm/rockchip: analogix_dp: introduce the pclk for grf
        drm/bridge: analogix_dp: fix no drm hpd event when panel plug in
        drm/rockchip: analogix_dp: update the comments about why need to hardcode VOP output mode
        drm/rockchip: analogix_dp: correct the connector display color format and bpc
        drm/bridge: analogix_dp: passing the connector as an argument in .get_modes()
        drm/rockchip: analogix_dp: make panel detect to an optional action
        drm/rockchip: analogix_dp: add rk3399 eDP support
        drm/bridge: analogix_dp: some rockchip chips need to flip REF_CLK bit setting
        drm/bridge: analogix_dp: correct the register bit define error in ANALOGIX_DP_PLL_REG_1
        drm/rockchip: analogix_dp: split the lcdc select setting into device data
      e2b80bac
    • Dave Airlie's avatar
      Merge tag 'imx-drm-next-2016-07-14' of git://git.pengutronix.de/git/pza/linux into drm-next · d3c35337
      Dave Airlie authored
      imx-drm updates
      
      - atomic mode setting conversion
      - replace DMFC FIFO allocation mechanism with a fixed allocation
        that is good enough for all cases
      - support for external bridges connected to parallel-display
      - improved error handling in imx-ldb, imx-tve, and parallel-display
      - some code cleanup in imx-tve
      
      * tag 'imx-drm-next-2016-07-14' of git://git.pengutronix.de/git/pza/linux:
        drm/imx: parallel-display: add bridge support
        drm/imx: parallel-display: check return code from of_get_drm_display_mode()
        gpu: ipu-v3: ipu-dc: don't bug out on invalid bus_format
        drm/imx: imx-tve: fix the error message
        drm/imx: imx-tve: remove unneeded 'or' operation
        drm/imx: imx-tve: check the value returned by regulator_set_voltage()
        drm/imx: imx-ldb: check return code on panel attach
        drm/imx: turn remaining container_of macros into inline functions
        drm/imx: store internal bus configuration in crtc state
        drm/imx: remove empty mode_set encoder callbacks
        drm/imx: atomic phase 3 step 3: Advertise DRIVER_ATOMIC
        drm/imx: atomic phase 3 step 2: Legacy callback fixups
        drm/bridge: dw-hdmi: Remove the legacy drm_connector_funcs structure
        drm/imx: atomic phase 3 step 1: Use atomic configuration
        drm/imx: Remove encoders' ->prepare callbacks
        drm/imx: atomic phase 2 step 2: Track plane_state->fb correctly in ->page_flip
        drm/imx: atomic phase 2 step 1: Wire up state ->reset, ->duplicate and ->destroy
        drm/imx: atomic phase 1: Use transitional atomic CRTC and plane helpers
        gpu: ipu-v3: ipu-dmfc: Use static DMFC FIFO allocation mechanism
        drm/imx: ipuv3 plane: Check different types of plane separately
      d3c35337
  2. 15 Jul, 2016 9 commits
    • Eric Anholt's avatar
      drm/vc4: Fix a "the the" typo in a comment. · a20d5fa6
      Eric Anholt authored
      Signed-off-by: default avatarEric Anholt <eric@anholt.net>
      a20d5fa6
    • Eric Anholt's avatar
      drm/vc4: Fix definition of QPU_R_MS_REV_FLAGS · 20e48fd6
      Eric Anholt authored
      We don't use it in shader validation currently, so it had no effect,
      but best to fix it anyway in case we do some day.
      Signed-off-by: default avatarEric Anholt <eric@anholt.net>
      20e48fd6
    • Eric Anholt's avatar
      drm/vc4: Add a getparam to signal support for branches. · 7363cee5
      Eric Anholt authored
      Userspace needs to know if it can create shaders that do branching.
      Otherwise, for backwards compatibility with old kernels it needs to
      lower if statements to conditional assignments.
      Signed-off-by: default avatarEric Anholt <eric@anholt.net>
      7363cee5
    • Eric Anholt's avatar
      drm/vc4: Add support for branching in shader validation. · 6d45c81d
      Eric Anholt authored
      We're already checking that branch instructions are between the start
      of the shader and the proper PROG_END sequence.  The other thing we
      need to make branching safe is to verify that the shader doesn't read
      past the end of the uniforms stream.
      
      To do that, we require that at any basic block reading uniforms have
      the following instructions:
      
      load_imm temp, <next offset within uniform stream>
      add unif_addr, temp, unif
      
      The instructions are generated by userspace, and the kernel verifies
      that the load_imm is of the expected offset, and that the add adds it
      to a uniform.  We track which uniform in the stream that is, and at
      draw call time fix up the uniform stream to have the address of the
      start of the shader's uniforms at that location.
      Signed-off-by: default avatarEric Anholt <eric@anholt.net>
      6d45c81d
    • Eric Anholt's avatar
      drm/vc4: Add a bitmap of branch targets during shader validation. · 93aa9ae3
      Eric Anholt authored
      This isn't used yet, it's just a first step toward loop validation.
      During the main parsing of instructions, we need to know when we hit a
      new basic block so that we can reset validated state.
      
      v2: Fix a stray semicolon after an if block.  (caught by kbuild test).
      Signed-off-by: default avatarEric Anholt <eric@anholt.net>
      93aa9ae3
    • Dave Airlie's avatar
      Merge branch 'exynos-drm-next' of... · f82c1372
      Dave Airlie authored
      Merge branch 'exynos-drm-next' of git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos into drm-next
      
         This pull request adds to the rework patch series for IOMMU
         integration to support ARM64bit architecture with DMA-IOMMU
         glue code.
      
         With this patch series, Exynos DRM works well on Exynos5433 SoC
         with IOMMU enabled.
      
      * 'exynos-drm-next' of git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos:
        drm/exynos: iommu: add support for ARM64 specific code for IOMMU glue
        drm/exynos: iommu: move ARM specific code to exynos_drm_iommu.h
        drm/exynos: iommu: remove unused entries from exynos_drm_private strcuture
        drm/exynos: iommu: add a check if all sub-devices have iommu controller
        drm/exynos: iommu: move dma_params configuration code to separate functions
      f82c1372
    • Dave Airlie's avatar
      Merge tag 'drm-vc4-next-2016-07-12' of https://github.com/anholt/linux into drm-next · 35b8a749
      Dave Airlie authored
      This pull request brings in new vc4 plane formats for Android, precise
      vblank timestamping, and a couple of small cleanups.
      
      * tag 'drm-vc4-next-2016-07-12' of https://github.com/anholt/linux:
        drm/vc4: remove redundant ret status check
        drm/vc4: Implement precise vblank timestamping.
        drm/vc4: Bind the HVS before we bind the individual CRTCs.
        gpu: drm: vc4_hdmi: add missing of_node_put after calling of_parse_phandle
        drm: vc4: enable XBGR8888 and ABGR8888 pixel formats
        drm/vc4: clean up error exit path on failed dpi_connector allocation
      35b8a749
    • Dave Airlie's avatar
      Merge tag 'drm-intel-next-2016-07-11' of git://anongit.freedesktop.org/drm-intel into drm-next · ff37c05a
      Dave Airlie authored
      - select igt testing depencies for CONFIG_DRM_I915_DEBUG (Chris)
      - track outputs in crtc state and clean up all our ad-hoc connector/encoder
        walking in modest code (Ville)
      - demidlayer drm_device/drm_i915_private (Chris Wilson)
      - thundering herd fix from Chris Wilson, with lots of help from Tvrtko Ursulin
      - piles of assorted clean and fallout from the thundering herd fix
      - documentation and more tuning for waitboosting (Chris)
      - pooled EU support on bxt (Arun Siluvery)
      - bxt support is no longer considered prelimary!
      - ring/engine vfunc cleanup from Tvrtko
      - introduce intel_wait_for_register helper (Chris)
      - opregion updates (Jani Nukla)
      - tuning and fixes for wait_for macros (Tvrkto&Imre)
      - more kabylake pci ids (Rodrigo)
      - pps cleanup and fixes for bxt (Imre)
      - move sink crc support over to atomic state (Maarten)
      - fix up async fbdev init ordering (Chris)
      - fbc fixes from Paulo and Chris
      
      * tag 'drm-intel-next-2016-07-11' of git://anongit.freedesktop.org/drm-intel: (223 commits)
        drm/i915: Update DRIVER_DATE to 20160711
        drm/i915: Select DRM_VGEM for igt
        drm/i915: Select X86_MSR for igt
        drm/i915: Fill unused GGTT with scratch pages for VT-d
        drm/i915: Introduce Kabypoint PCH for Kabylake H/DT.
        drm/i915:gen9: implement WaMediaPoolStateCmdInWABB
        drm/i915: Check for invalid cloning earlier during modeset
        drm/i915: Simplify hdmi_12bpc_possible()
        drm/i915: Kill has_dsi_encoder
        drm/i915: s/INTEL_OUTPUT_DISPLAYPORT/INTEL_OUTPUT_DP/
        drm/i915: Replace some open coded intel_crtc_has_dp_encoder()s
        drm/i915: Kill has_dp_encoder from pipe_config
        drm/i915: Replace manual lvds and sdvo/hdmi counting with intel_crtc_has_type()
        drm/i915: Unify intel_pipe_has_type() and intel_pipe_will_have_type()
        drm/i915: Add output_types bitmask into the crtc state
        drm/i915: Remove encoder type checks from MST suspend/resume
        drm/i915: Don't mark eDP encoders as MST capable
        drm/i915: avoid wait_for_atomic() in non-atomic host2guc_action()
        drm/i915: Group the irq breadcrumb variables into the same cacheline
        drm/i915: Wake up the bottom-half if we steal their interrupt
        ...
      ff37c05a
    • Dave Airlie's avatar
      Merge tag 'topic/drm-misc-2016-07-14' of git://anongit.freedesktop.org/drm-intel into drm-next · 6c181c82
      Dave Airlie authored
      I recovered dri-devel backlog from my vacation, more misc stuff:
      - of_put_node fixes from Peter Chen (not all yet)
      - more patches from Gustavo to use kms-native drm_crtc_vblank_* funcs
      - docs sphinxification from Lukas Wunner
      - bunch of fixes all over from Dan Carpenter
      - more follow up work from Chris register/unregister rework in various
        places
      - vgem dma-buf export (for writing testcases)
      - small things all over from tons of different people
      
      * tag 'topic/drm-misc-2016-07-14' of git://anongit.freedesktop.org/drm-intel: (52 commits)
        drm: Don't overwrite user ioctl arg unless requested
        dma-buf/sync_file: improve Kconfig description for Sync Files
        MAINTAINERS: add entry for the Sync File Framework
        drm: Resurrect atomic rmfb code
        drm/vgem: Use PAGE_KERNEL in place of x86-specific PAGE_KERNEL_IO
        qxl: silence uninitialized variable warning
        qxl: check for kmap failures
        vga_switcheroo: Sphinxify docs
        drm: Restore double clflush on the last partial cacheline
        gpu: drm: rockchip_drm_drv: add missing of_node_put after calling of_parse_phandle
        gpu: drm: sti_vtg: add missing of_node_put after calling of_parse_phandle
        gpu: drm: sti_hqvdp: add missing of_node_put after calling of_parse_phandle
        gpu: drm: sti_vdo: add missing of_node_put after calling of_parse_phandle
        gpu: drm: sti_compositor: add missing of_node_put after calling of_parse_phandle
        drm/tilcdc: use drm_crtc_handle_vblank()
        drm/rcar-du: use drm_crtc_handle_vblank()
        drm/nouveau: use drm_crtc_handle_vblank()
        drm/atmel: use drm_crtc_handle_vblank()
        drm/armada: use drm_crtc_handle_vblank()
        drm: make drm_vblank_count_and_time() static
        ...
      6c181c82
  3. 14 Jul, 2016 10 commits
    • Eric Anholt's avatar
      drm/vc4: Move validation's current/max ip into the validation struct. · d0566c2a
      Eric Anholt authored
      Reduces the argument count for some of the functions, and will be used
      more with the upcoming looping support.
      Signed-off-by: default avatarEric Anholt <eric@anholt.net>
      d0566c2a
    • Eric Anholt's avatar
      drm/vc4: Add a getparam ioctl for getting the V3D identity regs. · af713795
      Eric Anholt authored
      As I extend the driver to support different V3D revisions, userspace
      needs to know what version it's targeting.  This is most easily
      detected using the V3D identity registers.
      
      v2: Make sure V3D is runtime PM on when reading the registers.
      v3: Switch to a 64-bit param value (suggested by Rob Clark in review)
      Signed-off-by: default avatarEric Anholt <eric@anholt.net>
      Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> (v2)
      Reviewed-by: Rob Clark <robdclark@gmail.com> (v3, over irc)
      af713795
    • Thierry Reding's avatar
      drm/tegra: sor: Reject HDMI 2.0 modes · 64ea25c3
      Thierry Reding authored
      Enabling HDMI 2.0 modes requires extra programming and will not work
      with the current driver, so reject all those modes.
      Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
      64ea25c3
    • Jon Hunter's avatar
      drm/tegra: sor: Prepare for generic PM domain support · f8c79120
      Jon Hunter authored
      The SOR driver for Tegra requires the SOR power partition to be enabled.
      Now that Tegra supports the generic PM domain framework we manage the
      SOR power partition via this framework. However, the sequence for
      gating/ungating the SOR power partition requires that the SOR reset is
      asserted/de-asserted at the time the SOR power partition is
      gated/ungated, respectively. Now that the reset control core assumes
      that resets are exclusive, the Tegra generic PM domain code and the SOR
      driver cannot request the same reset unless we mark the reset as shared.
      Sharing resets will not work in this case because we cannot guarantee
      that the reset will be asserted/de-asserted at the appropriate time.
      Therefore, given that the Tegra generic PM domain code will handle the
      resets, do not request the reset in the SOR driver if the SOR device has
      a PM domain associated.
      Signed-off-by: default avatarJon Hunter <jonathanh@nvidia.com>
      Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
      f8c79120
    • Jon Hunter's avatar
      drm/tegra: dsi: Prepare for generic PM domain support · 64230aa0
      Jon Hunter authored
      The DSI driver for Tegra requires the SOR power partition to be enabled.
      Now that Tegra supports the generic PM domain framework we manage the
      SOR power partition via this framework. However, the sequence for
      gating/ungating the SOR power partition requires that the DSI reset is
      asserted/de-asserted at the time the SOR power partition is
      gated/ungated, respectively. Now that the reset control core assumes
      that resets are exclusive, the Tegra generic PM domain code and the DSI
      driver cannot request the same reset unless we mark the reset as shared.
      Sharing resets will not work in this case because we cannot guarantee
      that the reset will be asserted/de-asserted at the appropriate time.
      Therefore, given that the Tegra generic PM domain code will handle the
      resets, do not request the reset in the DSI driver if the DSI device has
      a PM domain associated.
      Signed-off-by: default avatarJon Hunter <jonathanh@nvidia.com>
      Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
      64230aa0
    • Thierry Reding's avatar
      drm/tegra: sor: Make XBAR configurable per SoC · 30b49435
      Thierry Reding authored
      Provide a per-SoC mapping of lanes which can be used to configure the
      XBAR.
      Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
      30b49435
    • Thierry Reding's avatar
      drm/tegra: sor: Use sor1_src clock to set parent for HDMI · 618dee39
      Thierry Reding authored
      When running in HDMI mode, the sor1 IP block needs to use the sor1_src
      as parent clock, and in turn configure the sor1_src to use pll_d2_out0
      as its parent.
      Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
      618dee39
    • Thierry Reding's avatar
      dt-bindings: display: tegra: Add source clock for SOR · 5d2304c1
      Thierry Reding authored
      The SOR clock can have various sources, with the most commonly used
      being the sor_safe, pll_d2_out0, pll_dp and sor_brick clocks. These
      are configured using a three level mux, of which the first 2 levels
      can be treated as one. The direct parents of the SOR clock are the
      sor_safe, sor_brick and sor_src clocks, whereas the pll_d2_out0 and
      pll_dp clocks can be selected as parents of the sor_src clock via a
      second mux.
      
      Previous generations of Tegra have only supported eDP and LVDS with
      the SOR, where LVDS was never used on publicly available hardware.
      Clocking for this only ever required the first level mux (to select
      between sor_safe and sor_brick).
      
      Tegra210 has a new revision of the SOR that supports HDMI and hence
      needs to support the second level mux to allow selecting pll_d2_out0
      as the SOR clock's parent. This second mux is knows as sor_src, and
      operating system software needs a reference to it in order to select
      the proper parent.
      Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
      5d2304c1
    • Thierry Reding's avatar
      drm/tegra: sor: Implement sor1_brick clock · b299221c
      Thierry Reding authored
      sor1_brick is a clock that can be used as a source for the sor1 clock.
      The registers to control the clock output are part of the sor1 IP block
      and hence the sor driver is the best place to implement it.
      Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
      b299221c
    • Philipp Zabel's avatar
      drm/imx: parallel-display: add bridge support · f140b0cc
      Philipp Zabel authored
      Add support for bridge chips connected externally to the i.MX
      DISP0/DISP1 DPI interfaces.
      Signed-off-by: default avatarPhilipp Zabel <p.zabel@pengutronix.de>
      f140b0cc