- 18 Dec, 2019 39 commits
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Qingqing Zhuo authored
YQ should be limited range for all cases. Signed-off-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Camille Cho authored
[Why] A hardcoded number is used today [How] Add definition for number of BL data points Signed-off-by:
Camille Cho <Camille.Cho@amd.com> Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Joshua Aberback authored
[Why] For some use cases we need to be able to adjust the maximum target bpp allowed by DSC policy. [How] New interface dc_dsc_policy_set_max_target_bpp_limit Signed-off-by:
Joshua Aberback <joshua.aberback@amd.com> Reviewed-by:
Nikola Cornij <Nikola.Cornij@amd.com> Acked-by:
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Aidan Yang authored
[Why] Integer scaling is applied to MPO planes when downscaling, MPO planes use variable taps and integer scaling sets taps=1 [How] Disable integer scaling on MPO planes, Disable integer scaling for downscaling planes Signed-off-by:
Aidan Yang <Aidan.Yang@amd.com> Reviewed-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
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Nicholas Kazlauskas authored
[Why] CW0 and CW1 need to use physical addressing mode for dcn20 and dcn21. The current code for dcn20 is using virtual. [How] We already program the DMCUB like this on dcn21 so we should just use the same sequence for both. Copy the dcn21 sequences into the dmjub_dcn20.c file and rename them. Signed-off-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
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Nicholas Kazlauskas authored
[Why] These values can differ per ASIC and should follow the full DC style register programming model. [How] Define a common list and fill in the common list separately for dcn20 and dcn21. Unlike DC we're not using designated initializers for better compiler compatibility since this resides in the DMUB service. Signed-off-by:
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Noah Abradjian authored
[Why] Lack of proper timing caused intermittent underflow on unplug external DP. A previous fix was invalid and caused S0i3 regression, so had to be reverted. [How] When unlocking pipe, wait for no pipes to have flip pending before unlocking. Signed-off-by:
Noah Abradjian <noah.abradjian@amd.com> Reviewed-by:
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abdoulaye berthe authored
Signed-off-by:
abdoulaye berthe <abdoulaye.berthe@amd.com> Reviewed-by:
George Shen <George.Shen@amd.com> Acked-by:
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Charlene Liu authored
Add HDMI 2.x audio bandwidth check Signed-off-by:
Chris Park <Chris.Park@amd.com> Acked-by:
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Leo Liu authored
For VCN2.0 and above, VCN has been separated from JPEG Signed-off-by:
Leo Liu <leo.liu@amd.com> Reviewed-by:
James Zhu <James.Zhu@amd.com> Signed-off-by:
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Leo Liu authored
Because VCN1.0 power management and DPG mode are managed together with JPEG1.0 under both HW and FW, so separated them from general VCN code. Also the multiple instances case got removed, since VCN1.0 HW just have a single instance. v2: override work func with vcn1.0's own Signed-off-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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changzhu authored
When smu version is larger than 0x41e2b, it will load raven_kicker_rlc.bin.To enable gfxoff for raven_kicker_rlc.bin,it needs to avoid adev->pm.pp_feature &= ~PP_GFXOFF_MASK when it loads raven_kicker_rlc.bin. Signed-off-by:
changzhu <Changfeng.Zhu@amd.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Acked-by:
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Emily Deng authored
Fix Tonga sriov load driver fail issue. Signed-off-by:
Emily Deng <Emily.Deng@amd.com> Reviewd-by Yintian Tao <Yintian.tao@amd.com> Signed-off-by:
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Guchun Chen authored
BACO reset mode strategy is determined by latter func when calling amdgpu_ras_reset_gpu. So not to confuse audience, drop it. Signed-off-by:
Guchun Chen <guchun.chen@amd.com> Reviewed-by:
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Roman Li authored
[Why] The earlier change: "check phy dpalt lane count config" uses link encoder registers not defined properly. That caused regression with mst-enabled display not lighting up. [How] Add missing reg definitions. Signed-off-by:
Roman Li <Roman.Li@amd.com> Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Roman Li authored
add reg headers to dpcs includes Signed-off-by:
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Roman Li authored
- create dpcs directory for dpcs asic_reg headers - move dpcs21 reg headers from dcn to dpcs directory Signed-off-by:
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Yong Zhao authored
The log will be useful for easily getting the CU info on various emulation models or ASICs. Signed-off-by:
Yong Zhao <Yong.Zhao@amd.com> Reviewed-by:
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Yong Zhao authored
Since Arcturus has it own function pointer, we can move Arcturus specific logic to there rather than leaving it entangled with other GFX9 chips. Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Colin Ian King authored
There are several occurrances of the pointer hwmgr being dereferenced before it is null checked. Fix these by performing the dereference of hwmgr after it has been null checked. Addresses-Coverity: ("Dereference before null check") Fixes: c9ffa427 ("drm/amd/powerplay: enable pp one vf mode for vega10") Signed-off-by:Colin Ian King <colin.king@canonical.com> Signed-off-by:
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Philip Yang authored
Because queue_work schedule the work on the same CPU the interrupt handler is running, if there are many interrupts pending, it takes longer time for work queue to start, or even worse system will hang. v2: queue work to same NUMA node for better cache locality v3: handle cpumask_next wraparound case Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Reviewed-by:
Eric Huang <JinhuiEric.Huang@amd.com> Signed-off-by:
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Timothy Pearson authored
dc20 containes several FPU-dependent functions without proper FPU kernel mode enable/disable wrappers. Add the required wrappers for both x86 and POWER. This enables Navi DC20 support for POWER systems. v2: fix compilation Signed-off-by:
Timothy Pearson <tpearson@raptorengineering.com> Signed-off-by:
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Timothy Pearson authored
DCN requires floating point support to operate. Add the appropriate x86/ppc64 guards and FPU / AltiVec / VSX context switches to DCN. Note that the current DC20 code doesn't contain all required FPU wrappers on x86 or POWER, so this patch is insufficient to fully enable DC20 on POWER. v2: s/X86_64/X86/g to retain previous behavior. Signed-off-by:
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Timothy Pearson authored
Introduce DC_FP_START()/DC_FP_END() macros to help enable floating point kernel mode support across various architectures. v2: move copyright update to commit which adds the changes Signed-off-by:
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git://linuxtv.org/pinchartl/mediaDaniel Vetter authored
R-Car Display Unit changes: - Color Management Module support - LVDS encoder dual-link support enhancements - R8A77980 support Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch> From: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191218151710.GA13830@pendragon.ideasonboard.com
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Kieran Bingham authored
Add direct support for the r8a77980 (V3H). The V3H shares a common, compatible configuration with the r8a77970 (V3M) so that device info structure is reused. Signed-off-by:
Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Reviewed-by:
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by:
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Fabrizio Castro authored
DT properties dual-lvds-even-pixels and dual-lvds-odd-pixels can be used to work out if the driver needs to swap even and odd pixels around. This patch makes use of the return value from function drm_of_lvds_get_dual_link_pixel_order to determine if we need to swap odd and even pixels around for things to work properly. The dual_link boolean field from struct rcar_lvds is not sufficient to describe the type of LVDS link anymore, since we now have information related to pixel order, therefore rename it to link_type and repurpose its usage to fit the new requirements. Signed-off-by:
Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by:
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Fabrizio Castro authored
For dual-LVDS configurations, it is now possible to mark the DT port nodes for the sink with boolean properties (like dual-lvds-even-pixels and dual-lvds-odd-pixels) to let drivers know the encoders need to be configured in dual-LVDS mode. Rework the implementation of rcar_lvds_parse_dt_companion to make use of the DT markers while keeping backward compatibility. Signed-off-by:
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Fabrizio Castro authored
Dual-LVDS panels are mistakenly identified as bridges, this commit replaces the current logic with a call to drm_of_find_panel_or_bridge to sort that out. Signed-off-by:
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Fabrizio Castro authored
An LVDS dual-link connection is made of two links, with even pixels transitting on one link, and odd pixels on the other link. The device tree can be used to fully describe dual-link LVDS connections between encoders and bridges/panels. The sink of an LVDS dual-link connection is made of two ports, the corresponding OF graph port nodes can be marked with either dual-lvds-even-pixels or dual-lvds-odd-pixels, and that fully describes an LVDS dual-link connection, including pixel order. drm_of_lvds_get_dual_link_pixel_order is a new helper added by this patch, given the source port nodes it returns DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS if the source port nodes belong to an LVDS dual-link connection, with even pixels expected to be generated from the first port, and odd pixels expected to be generated from the second port. If the new helper returns DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS, odd pixels are expected to be generated from the first port, and even pixels from the other port. Signed-off-by:
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Laurent Pinchart authored
The R-Car LVDS encoder driver implements the bridge .mode_set() operation for the sole purpose of storing the mode in the LVDS private data, to be used later when enabling the encoder. Switch to the bridge .atomic_enable() and .atomic_disable() operations in order to access the global atomic state, and get the mode from the state instead. Remove both the unneeded .mode_set() operation and the display_mode and mode fields storing state data from the rcar_lvds private structure. As a side effect we get the CRTC from the state, replace the CRTC pointer retrieved through the bridge's encoder that shouldn't be used by atomic drivers. While at it, clarify a few error messages in rcar_lvds_get_lvds_mode() and turn them into warnings as they are not fatal. Signed-off-by:
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Geert Uytterhoeven authored
The Renesas-specific "vsps" property lacks a vendor prefix. Add a "renesas," prefix to comply with DT best practises. Retain backward compatibility with old DTBs by falling back to "vsps" when needed. Fixes: 6d62ef3a ("drm: rcar-du: Expose the VSP1 compositor through KMS planes") Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by:
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Geert Uytterhoeven authored
The Renesas-specific "vsps" property lacks a vendor prefix. Add a "renesas," prefix to comply with DT best practises. Move "renesas,vsps" below "renesas,cmms" to preserve alphabetical sort order. Fixes: 06711e63 ("drm: rcar-du: Document the vsps property in the DT bindings") Signed-off-by:
Rob Herring <robh@kernel.org> Reviewed-by:
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Jacopo Mondi authored
Enable the GAMMA_LUT KMS property using the framework helpers to register the property and set the associated gamma table maximum size. Reviewed-by:
Ulrich Hecht <uli+renesas@fpond.eu> Reviewed-by:
Jacopo Mondi <jacopo+renesas@jmondi.org> Signed-off-by:
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Jacopo Mondi authored
Implement CMM handling in the crtc begin and enable atomic callbacks, and enable CMM unit through the Display Extensional Functions register at group setup time. Reviewed-by:
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Jacopo Mondi authored
Implement device tree parsing to collect the available CMM instances described by the 'renesas,cmms' property. Associate CMMs with CRTCs and store a mask of active CMMs in the DU group for later enablement. Enforce the probe and suspend/resume ordering of DU and CMM by creating a stateless device link between the two. Reviewed-by:
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Jacopo Mondi authored
Add a driver for the R-Car Display Unit Color Correction Module. In most of Gen3 SoCs, each DU output channel is provided with a CMM unit to perform image enhancement and color correction. Add support for CMM through a driver that supports configuration of the 1-dimensional LUT table. More advanced CMM features will be implemented on top of this initial one. Reviewed-by:
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Jacopo Mondi authored
Document the newly added 'renesas,cmms' property which accepts a list of phandle and channel index pairs that point to the CMM units available for each Display Unit output video channel. Reviewed-by:
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Jacopo Mondi authored
Add device tree bindings documentation for the Renesas R-Car Display Unit Color Management Module. CMM is the image enhancement module available on each R-Car DU video channel on R-Car Gen2 and Gen3 SoCs (V3H and V3M excluded). Reviewed-by:
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- 17 Dec, 2019 1 commit
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git://people.freedesktop.org/~agd5f/linuxDaniel Vetter authored
drm-next-5.6-2019-12-11: amdgpu: - Add MST atomic routines - Add support for DMCUB (new helper microengine for displays) - Add OEM i2c support in DC - Use vstartup for vblank events on DCN - Simplify Kconfig for DC - Renoir fixes for DC - Clean up function pointers in DC - Initial support for HDCP 2.x - Misc code cleanups - GFX10 fixes - Rework JPEG engine handling for VCN - Add clock and power gating support for JPEG - BACO support for Arcturus - Cleanup PSP ring handling - Add framework for using BACO with runtime pm to save power - Move core pci state handling out of the driver for pm ops - Allow guest power control in 1 VF case with SR-IOV - SR-IOV fixes - RAS fixes - Support for power metrics on renoir - Golden settings updates for gfx10 - Enable gfxoff on supported navi10 skus - Update MAINTAINERS amdkfd: - Clean up generational gfx code - Fixes for gfx10 - DIQ fixes - Share more code with amdgpu radeon: - PPC DMA fix - Register checker fixes for r1xx/r2xx - Misc cleanups From: Alex Deucher <alexdeucher@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191211223020.7510-1-alexander.deucher@amd.com
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