- 01 Jul, 2020 40 commits
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Likun Gao authored
Add support to force and unforce MCLK or SOCCLK to dpm limit value. Signed-off-by:
Likun Gao <Likun.Gao@amd.com> Reviewed-by:
Kenneth Feng <kenneth.feng@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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shaoyunl authored
This is a regression due to the rebase , add sienna_cichlid sriov detection back Signed-off-by:
shaoyunl <shaoyun.liu@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Likun Gao authored
Only enable one gfx pipe for sienna_cichlid currently. Signed-off-by:
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Likun Gao authored
VCN removed JPEG for instance 1, so drop jpeg instance1 dpm setup. Signed-off-by:
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Likun Gao authored
Disable runtime pm for sienna_cichlid temporarily as BACO regression issue. Signed-off-by:
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Kenneth Feng authored
fw ctf can be triggered if the temperature can't be throttled below the limit. then the gpu will be powered off and the whole system will hang. Signed-off-by:
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Likun Gao authored
Fix the coding error to skip GPU scheduler setup for KIQ and MES ring. Signed-off-by:
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Likun Gao authored
Enable VDDCI and MVDD if PP_MCLK_DPM_MASK was enable for sienna_cichlid. Signed-off-by:
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Likun Gao authored
Add function to append powerplay table from vbios for sienna_cichlid. v2: squash in warning fix Signed-off-by:
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Likun Gao authored
And atom_smc_dpm_info_v4_9 struct for sienna_cichlid use. Signed-off-by:
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shaoyunl authored
On SRIOV run time, driver shouldn't directly access invalidation registers through MMIO. Use kiq to submit wait_reg_mem package for the invalidation Signed-off-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Likun Gao authored
Enable uclk deep sleep for sienna_cichlid. Df cstate kicks in first, then df triggers uclk ds with the sideband. Signed-off-by:
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Alex Deucher authored
VCN3 has 2 unsymmetrical instances, i.e there're less codecs on instance 1, we use 0 for decode and 1 for encode for now Reviewed-by:
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Alex Deucher authored
We don't want a gpu scheduler for mes. Reviewed-by:
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Boyuan Zhang authored
Enable DPG mode for VCN3.0 by updating related flag. V2: update description. Signed-off-by:
Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by:
James Zhu <james.zhu@amd.com> Reviewed-by:
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Boyuan Zhang authored
To workaround an issue in DPG V2: update description. Signed-off-by:
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Boyuan Zhang authored
Rename SOC15_DPG_MODE_OFFSET_2_0, RREG32_SOC15_DPG_MODE_2_0 and WREG32_SOC15_DPG_MODE_2_0 for VCN2.0, VCN2.5 and VCN3.0. These three macros are used VCN2.0, VCN2.5 and VCN3.0, therefore rename it to be a general name. Signed-off-by:
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Boyuan Zhang authored
Rename RREG32_SOC15_DPG_MODE and WREG32_SOC15_DPG_MODE for VCN1.0 These two macros are used specifically for VCN1.0, therefore rename it from general name to VCN1.0 specific name. Signed-off-by:
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Boyuan Zhang authored
Add range for vcn instance 1 for translation for internal register offset, which is needed for VCN3.0 V2: update description. Signed-off-by:
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Boyuan Zhang authored
Use indirect sram for secure DPG mode V2: update description. Signed-off-by:
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Boyuan Zhang authored
Add vcn_v3_0_pause_dpg_mode to pause/unpause DPG mode for VCN3.0 V2: update description. Signed-off-by:
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Boyuan Zhang authored
Add vcn_v3_0_stop_dpg_mode to power off in DPG mode for VCN3.0 V2: update description. Signed-off-by:
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Boyuan Zhang authored
Add vcn_v3_0_start_dpg_mode to setup and start VCN block in DPG mode for VCN3.0 V2: Separate from previous patch-0002, and update description. Signed-off-by:
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Boyuan Zhang authored
Add vcn_v3_0_mc_resume_dpg_mode to resume memory controller in DPG mode for VCN3.0 V2: Separate from previous patch-0002, and update description. Signed-off-by:
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Boyuan Zhang authored
Add vcn_v3_0_clock_gating_dpg_mode to enabling clock gating in DPG mode for VCN3.0 V2: Separate from previous patch-0002, and update description. Signed-off-by:
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Likun Gao authored
Enable OUT OF BAND MONITER for sienna_cichlid. Signed-off-by:
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Likun Gao authored
Enable RSMU SMN PG for sienna_cichlid. Signed-off-by:
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Likun Gao authored
Update golden setting for sienna_cichlid. Signed-off-by:
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Kenneth Feng authored
Bundle GPO with gfx DPM and enable it since gfxclk dpm should work first then GPO works. Signed-off-by:
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Kenneth Feng authored
GPO is graphics power optimizer. SMU calculates the 16 gfxclk V/F points according to the CU numbers and memory activity.RLC picks one of them according to the memory speed requirements for the data transmission. Signed-off-by:
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Kenneth Feng authored
mmhub pg can be obvserved from PCTL_CTRL Signed-off-by:
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Kenneth Feng authored
enable athub pg and the status can be checked in ATHUB_MISC_CNTL. Signed-off-by:
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Le Ma authored
Statically allocated VM inv eng of gfxhub on sienna_cichlid is used up. Also VM inv eng is no need for mes ring. Signed-off-by:
Le Ma <le.ma@amd.com> Reviewed-by:
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Le Ma authored
Pass a piece of memory to MES ucode to fill contents. Signed-off-by:
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Le Ma authored
Update for new member query_status_fence_gpu_mc_ptr in MESAPI_SET_HW_RESOURCES. Signed-off-by:
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Le Ma authored
Update mes_api_def.h to match the latest mes fw. v2: clean up coding style based on kernel standards: - fix indentation and alignment - break long lines - put the opening brace last on the line - remove unnecessary blank line and space - replace uint(32|64) with standard uint(32|64)_t Signed-off-by:
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Likun Gao authored
Add function to get pptable power limit for sienna_cichlid. Signed-off-by:
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Likun Gao authored
Enable APCC DFLL for sienna_cichlid. Signed-off-by:
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Likun Gao authored
Enable BACO for sienna_cichlid. Signed-off-by:
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shaoyunl authored
SMU firmware already been loaded from host, don't enable it for now. May need to re-work it if we want to enable the SMU for guest in the future. Signed-off-by:
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