- 04 Jun, 2015 40 commits
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Christian König authored
Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com>
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Christian König authored
Signed-off-by:
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Christian König authored
Deny user and kernel mapping if we said we never want to do so. Signed-off-by:
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Christian König authored
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Alex Deucher authored
Retry the dpcd fetch several times. Some eDP panels fail several times before the fetch is successful. bug: https://bugs.freedesktop.org/show_bug.cgi?id=73530 Ported from radeon. Reviewed-by:
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Alex Deucher authored
Use %*ph rather than walking the array. Reviewed-by:
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Alex Deucher authored
Ported from similar radeon patch. Reviewed-by:
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Alex Deucher authored
Since we may modify display state. Reviewed-by:
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Marek Olšák authored
Signed-off-by:
Marek Olšák <marek.olsak@amd.com> Reviewed-by:
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Alex Deucher authored
Reviewed-by:
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Alex Deucher authored
Reviewed-by:
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Jammy Zhou authored
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Jammy Zhou authored
v2: keep using radeon folder for CIK Signed-off-by:
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Jammy Zhou authored
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Jammy Zhou authored
Signed-off-by:
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Christian König authored
Properly protect the state and also handle submission failures. Signed-off-by:
Monk Liu <monk.liu@amd.com>
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Christian König authored
Signed-off-by:
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Christian König authored
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Christian König authored
Otherwise a process can access the GDS data of another process. Signed-off-by:
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Jammy Zhou authored
The CE preamble IB can be dropped for the same context v2: use the flags directly v3: remove 'CE' for potential preamble usage by other rings Signed-off-by:
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Jammy Zhou authored
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Jammy Zhou authored
check the filp is not robust, and sometimes different contexts may have same filp value. v2: check both filp and ctx_id Signed-off-by:
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Jammy Zhou authored
It is required to support fence per context. v2: add amdgpu_ctx_get/put v3: improve get/put v4: squash hlock fix Signed-off-by:
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Jack Xiao authored
Set up the CP and SDMA for proper unaligned memory access. Required for OpenCL 2.x v2: udpate commit message Signed-off-by:
Jack Xiao <Jack.Xiao@amd.com> Reviewed-by:
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Marek Olšák authored
The existing locks were protecting the list, but not the elements. v2: rename hlock to lock Signed-off-by:
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Marek Olšák authored
If ctx was released between put and get, then "get" would crash. Signed-off-by:
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Christian König authored
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monk.liu authored
sg could point to array of contigiouse page*, only free page could lead to memory leak. v2: use iterator Signed-off-by:
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Jammy Zhou authored
This flag isn't used by user mode drivers, remove it to avoid confusion. And rename GTT_WC to GTT_USWC to make it clear. Signed-off-by:
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Sonny Jiang authored
Fix crash when disabling dpm. v2: agd5f: fix coding style, cleanup commit message Signed-off-by:
Sonny Jiang <sonny.jiang@amd.com> Reviewed-by:
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Alex Deucher authored
Avoids possibility that info may leak via the uninitialized _pad element. Noticed-by:
Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by:
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Alex Deucher authored
Need to unlock the mutex on error. Noticed-by:
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monk.liu authored
this could prevent mis-understanding, because libdrm side will consider no bo_list created if handleis zero Signed-off-by:
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monk.liu authored
Still need to handle ibs BO and validate them even bo_list is NULL Signed-off-by:
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Jack Xiao authored
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Alex Deucher authored
amdgpu_bo_create() calls amdgpu_ttm_placement_from_domain() before ttm_bo_init() is called. amdgpu_ttm_placement_from_domain() uses the ttm bo size to determine when to select top down allocation but since the ttm bo is not initialized yet the check is always false. It only took affect when buffers were validated later. It also seemed to regress suspend and resume on some systems possibly due to it not taking affect in amdgpu_bo_create(). amdgpu_bo_create() and amdgpu_ttm_placement_from_domain() need to be reworked substantially for this to be optimally effective. Re-enable it at that point. Ported from radeon commit: a239118aSigned-off-by:
Michel Dänzer <michel.daenzer@amd.com> Reviewed-by:
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Alex Deucher authored
Acked-by:
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Alex Deucher authored
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Alex Deucher authored
This adds initial support for VI asics. This includes Iceland, Tonga, and Carrizo. Our inital focus as been Carrizo, so there are still gaps in support for Tonga and Iceland, notably power management. Acked-by:
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Alex Deucher authored
This patch adds support for CIK parts. These parts are also supported by radeon which is the preferred option, so there is a config option to enable support for CIK parts in amdgpu for testing. Acked-by:
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