1. 08 May, 2010 1 commit
  2. 07 May, 2010 1 commit
    • Ky Srinivasan's avatar
      x86: Detect running on a Microsoft HyperV system · a2a47c6c
      Ky Srinivasan authored
      This patch integrates HyperV detection within the framework currently
      used by VmWare. With this patch, we can avoid having to replicate the
      HyperV detection code in each of the Microsoft HyperV drivers.
      
      Reworked and tweaked by Greg K-H to build properly.
      Signed-off-by: default avatarK. Y. Srinivasan <ksrinivasan@novell.com>
      LKML-Reference: <20100506190841.GA1605@kroah.com>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Ingo Molnar <mingo@redhat.com>
      Cc: "H. Peter Anvin" <hpa@zytor.com>
      Cc: Vadim Rozenfeld <vrozenfe@redhat.com>
      Cc: Avi Kivity <avi@redhat.com>
      Cc: Gleb Natapov <gleb@redhat.com>
      Cc: Frederic Weisbecker <fweisbec@gmail.com>
      Cc: Alexey Dobriyan <adobriyan@gmail.com>
      Cc: "K.Prasad" <prasad@linux.vnet.ibm.com>
      Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
      Cc: Stephane Eranian <eranian@google.com>
      Cc: Paul Mackerras <paulus@samba.org>
      Cc: Alan Cox <alan@linux.intel.com>
      Cc: Haiyang Zhang <haiyangz@microsoft.com>
      Cc: Hank Janssen <hjanssen@microsoft.com>
      Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
      Signed-off-by: default avatarH. Peter Anvin <hpa@zytor.com>
      a2a47c6c
  3. 03 May, 2010 2 commits
  4. 23 Apr, 2010 5 commits
    • Borislav Petkov's avatar
      x86, cacheinfo: Disable index in all four subcaches · 59d3b388
      Borislav Petkov authored
      When disabling an L3 cache index, make sure we disable that index in
      all four subcaches of the L3. Clarify nomenclature while at it, wrt to
      disable slots versus disable index and rename accordingly.
      Signed-off-by: default avatarBorislav Petkov <borislav.petkov@amd.com>
      LKML-Reference: <1271945222-5283-6-git-send-email-bp@amd64.org>
      Signed-off-by: default avatarH. Peter Anvin <hpa@zytor.com>
      59d3b388
    • Borislav Petkov's avatar
      x86, cacheinfo: Make L3 cache info per node · ba06edb6
      Borislav Petkov authored
      Currently, we're allocating L3 cache info and calculating indices for
      each online cpu which is clearly superfluous. Instead, we need to do
      this per-node as is each L3 cache.
      
      No functional change, only per-cpu memory savings.
      
      -v2: Allocate L3 cache descriptors array dynamically.
      Signed-off-by: default avatarBorislav Petkov <borislav.petkov@amd.com>
      LKML-Reference: <1271945222-5283-5-git-send-email-bp@amd64.org>
      Signed-off-by: default avatarH. Peter Anvin <hpa@zytor.com>
      ba06edb6
    • Borislav Petkov's avatar
      x86, cacheinfo: Reorganize AMD L3 cache structure · 9350f982
      Borislav Petkov authored
      Add a struct representing L3 cache attributes (subcache sizes and
      indices count) and move the respective members out of _cpuid4_info.
      Also, stash the struct pci_dev ptr into the struct simplifying the code
      even more.
      
      There should be no functionality change resulting from this patch except
      slightly slimming the _cpuid4_info per-cpu vars.
      Signed-off-by: default avatarBorislav Petkov <borislav.petkov@amd.com>
      LKML-Reference: <1271945222-5283-4-git-send-email-bp@amd64.org>
      Signed-off-by: default avatarH. Peter Anvin <hpa@zytor.com>
      9350f982
    • Frank Arnold's avatar
      x86, cacheinfo: Turn off L3 cache index disable feature in virtualized environments · f2b20e41
      Frank Arnold authored
      When running a quest kernel on xen we get:
      
      BUG: unable to handle kernel NULL pointer dereference at 0000000000000038
      IP: [<ffffffff8142f2fb>] cpuid4_cache_lookup_regs+0x2ca/0x3df
      PGD 0
      Oops: 0000 [#1] SMP
      last sysfs file:
      CPU 0
      Modules linked in:
      
      Pid: 0, comm: swapper Tainted: G        W  2.6.34-rc3 #1 /HVM domU
      RIP: 0010:[<ffffffff8142f2fb>]  [<ffffffff8142f2fb>] cpuid4_cache_lookup_regs+0x
      2ca/0x3df
      RSP: 0018:ffff880002203e08  EFLAGS: 00010046
      RAX: 0000000000000000 RBX: 0000000000000003 RCX: 0000000000000060
      RDX: 0000000000000000 RSI: 0000000000000040 RDI: 0000000000000000
      RBP: ffff880002203ed8 R08: 00000000000017c0 R09: ffff880002203e38
      R10: ffff8800023d5d40 R11: ffffffff81a01e28 R12: ffff880187e6f5c0
      R13: ffff880002203e34 R14: ffff880002203e58 R15: ffff880002203e68
      FS:  0000000000000000(0000) GS:ffff880002200000(0000) knlGS:0000000000000000
      CS:  0010 DS: 0000 ES: 0000 CR0: 000000008005003b
      CR2: 0000000000000038 CR3: 0000000001a3c000 CR4: 00000000000006f0
      DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
      DR3: 0000000000000000 DR6: 00000000ffff0ff0 DR7: 0000000000000400
      Process swapper (pid: 0, threadinfo ffffffff81a00000, task ffffffff81a44020)
      Stack:
       ffffffff810d7ecb ffff880002203e20 ffffffff81059140 ffff880002203e30
      <0> ffffffff810d7ec9 0000000002203e40 000000000050d140 ffff880002203e70
      <0> 0000000002008140 0000000000000086 ffff880040020140 ffffffff81068b8b
      Call Trace:
       <IRQ>
       [<ffffffff810d7ecb>] ? sync_supers_timer_fn+0x0/0x1c
       [<ffffffff81059140>] ? mod_timer+0x23/0x25
       [<ffffffff810d7ec9>] ? arm_supers_timer+0x34/0x36
       [<ffffffff81068b8b>] ? hrtimer_get_next_event+0xa7/0xc3
       [<ffffffff81058e85>] ? get_next_timer_interrupt+0x19a/0x20d
       [<ffffffff8142fa23>] get_cpu_leaves+0x5c/0x232
       [<ffffffff8106a7b1>] ? sched_clock_local+0x1c/0x82
       [<ffffffff8106a9a0>] ? sched_clock_tick+0x75/0x7a
       [<ffffffff8107748c>] generic_smp_call_function_single_interrupt+0xae/0xd0
       [<ffffffff8101f6ef>] smp_call_function_single_interrupt+0x18/0x27
       [<ffffffff8100a773>] call_function_single_interrupt+0x13/0x20
       <EOI>
       [<ffffffff8143c468>] ? notifier_call_chain+0x14/0x63
       [<ffffffff810295c6>] ? native_safe_halt+0xc/0xd
       [<ffffffff810114eb>] ? default_idle+0x36/0x53
       [<ffffffff81008c22>] cpu_idle+0xaa/0xe4
       [<ffffffff81423a9a>] rest_init+0x7e/0x80
       [<ffffffff81b10dd2>] start_kernel+0x40e/0x419
       [<ffffffff81b102c8>] x86_64_start_reservations+0xb3/0xb7
       [<ffffffff81b103c4>] x86_64_start_kernel+0xf8/0x107
      Code: 14 d5 40 ff ae 81 8b 14 02 31 c0 3b 15 47 1c 8b 00 7d 0e 48 8b 05 36 1c 8b
       00 48 63 d2 48 8b 04 d0 c7 85 5c ff ff ff 00 00 00 00 <8b> 70 38 48 8d 8d 5c ff
       ff ff 48 8b 78 10 ba c4 01 00 00 e8 eb
      RIP  [<ffffffff8142f2fb>] cpuid4_cache_lookup_regs+0x2ca/0x3df
       RSP <ffff880002203e08>
      CR2: 0000000000000038
      ---[ end trace a7919e7f17c0a726 ]---
      
      The L3 cache index disable feature of AMD CPUs has to be disabled if the
      kernel is running as guest on top of a hypervisor because northbridge
      devices are not available to the guest. Currently, this fixes a boot
      crash on top of Xen. In the future this will become an issue on KVM as
      well.
      
      Check if northbridge devices are present and do not enable the feature
      if there are none.
      Signed-off-by: default avatarFrank Arnold <frank.arnold@amd.com>
      LKML-Reference: <1271945222-5283-3-git-send-email-bp@amd64.org>
      Acked-by: default avatarBorislav Petkov <borislav.petkov@amd.com>
      Signed-off-by: default avatarH. Peter Anvin <hpa@zytor.com>
      f2b20e41
    • Borislav Petkov's avatar
      x86, cacheinfo: Unify AMD L3 cache index disable checking · b1ab1b4d
      Borislav Petkov authored
      All F10h CPUs starting with model 8 resp. 9, stepping 1, support L3
      cache index disable. Concentrate the family, model, stepping checking at
      one place and enable the feature implicitly on upcoming Fam10h models.
      Signed-off-by: default avatarBorislav Petkov <borislav.petkov@amd.com>
      LKML-Reference: <1271945222-5283-2-git-send-email-bp@amd64.org>
      Signed-off-by: default avatarH. Peter Anvin <hpa@zytor.com>
      b1ab1b4d
  5. 09 Apr, 2010 6 commits
  6. 30 Mar, 2010 6 commits
  7. 29 Mar, 2010 19 commits