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  1. 01 Dec, 2006 11 commits
    • John Keller's avatar
      Altix: Initial ACPI support - ROM shadowing. · a2302c68
      John Keller authored 
      Support a shadowed ROM when running with an ACPI capable PROM.

Define a new dev.resource flag IORESOURCE_ROM_BIOS_COPY to
describe the case of a BIOS shadowed ROM, which can then
be used to avoid pci_map_rom() making an unneeded call to
pci_enable_rom().
Signed-off-by: default avatarJohn Keller <jpk@sgi.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
      a2302c68
    • John Keller's avatar
      Altix: SN ACPI hotplug support. · 9f581f16
      John Keller authored 
      A few minor changes to the way slot/device fixup is done.

No need to be calling sn_pci_controller_fixup(), as
a root bus cannot be hotplugged.
Signed-off-by: default avatarJohn Keller <jpk@sgi.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
      9f581f16
    • John Keller's avatar
      Altix: Add initial ACPI IO support · 8ea6091f
      John Keller authored 
      First phase in introducing ACPI support to SN.
In this phase, when running with an ACPI capable PROM,
the DSDT will define the root busses and all SN nodes
(SGIHUB, SGITIO). An ACPI bus driver will be registered
for the node devices, with the acpi_pci_root_driver being
used for the root busses. An ACPI vendor descriptor is
now used to pass platform specific information for both
nodes and busses, eliminating the need for the current
SAL calls. Also, with ACPI support, SN fixup code is no longer
needed to initiate the PCI bus scans, as the acpi_pci_root_driver
does that.

However, to maintain backward compatibility with non-ACPI capable
PROMs, none of the current 'fixup' code can been deleted, though
much restructuring has been done. For example, the bulk of the code
in io_common.c is relocated code that is now common regardless
of what PROM is running, while io_acpi_init.c and io_init.c contain
routines specific to an ACPI or non ACPI capable PROM respectively.

A new pci bus fixup platform vector has been created to provide
a hook for invoking platform specific bus fixup from pcibios_fixup_bus().

The size of io_space[] has been increased to support systems with
large IO configurations.
Signed-off-by: default avatarJohn Keller <jpk@sgi.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
      8ea6091f
    • Matthew Wilcox's avatar
      PCI: Delete unused extern in powermac/pci.c · e08cf02f
      Matthew Wilcox authored 
      This file no longer uses pci_cache_line_size, so delete the declaration
Signed-off-by: default avatarMatthew Wilcox <matthew@wil.cx>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Acked-by: default avatarJeff Garzik <jeff@garzik.org>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
      e08cf02f
    • Matthew Wilcox's avatar
      PCI: Replace HAVE_ARCH_PCI_MWI with PCI_DISABLE_MWI · edb2d97e
      Matthew Wilcox authored 
      pSeries is the only architecture left using HAVE_ARCH_PCI_MWI and it's
really inappropriate for its needs.  It really wants to disable MWI
altogether.  So here are a pair of stub implementations for pci_set_mwi
and pci_clear_mwi.

Also rename pci_generic_prep_mwi to pci_set_cacheline_size since that
better reflects what it does.
Signed-off-by: default avatarMatthew Wilcox <matthew@wil.cx>
Cc: Paul Mackerras <paulus@samba.org>
Acked-by: default avatarJeff Garzik <jeff@garzik.org>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
      edb2d97e
    • Matthew Wilcox's avatar
      PCI: Use pci_generic_prep_mwi on sparc64 · ebf5a248
      Matthew Wilcox authored 
      The setting of the CACHE_LINE_SIZE register in sparc64's pci
initialisation code isn't quite adequate as the device may have
incompatible requirements.  The generic code tests for this, so switch
sparc64 over to using it.

Since sparc64 has different L1 cache line size and PCI cache line size,
it would need to override the generic code like i386 and ia64 do.  We
know what the cache line size is at compile time though, so introduce a
new optional constant PCI_CACHE_LINE_BYTES.
Signed-off-by: default avatarMatthew Wilcox <matthew@wil.cx>
Signed-off-by: default avatarDavid Miller <davem@davemloft.net>
Acked-by: default avatarJeff Garzik <jeff@garzik.org>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
      ebf5a248
    • Matthew Wilcox's avatar
      PCI: Use pci_generic_prep_mwi on ia64 · 3efe2d84
      Matthew Wilcox authored 
      The pci_generic_prep_mwi() code does everything that pcibios_prep_mwi()
does on ia64.  All we need to do is be sure that pci_cache_line_size
is set appropriately, and we can delete pcibios_prep_mwi().

Using SMP_CACHE_BYTES as the default was wrong on uniprocessor machines
as it is only 8 bytes.  The default in the generic code of L1_CACHE_BYTES
is at least as good.
Signed-off-by: default avatarMatthew Wilcox <matthew@wil.cx>
Acked-by: default avatarJeff Garzik <jeff@garzik.org>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
      3efe2d84
    • Alan Cox's avatar
      PCI: quirks: fix the festering mess that claims to handle IDE quirks · 368c73d4
      Alan Cox authored 
      The number of permutations of crap we do is amazing and almost all of it
has the wrong effect in 2.6.

At the heart of this is the PCI SFF magic which says that compatibility
mode PCI IDE controllers use ISA IRQ routing and hard coded addresses
not the BAR values. The old quirks variously clears them, sets them,
adjusts them and then IDE ignores the result.

In order to drive all this garbage out and to do it portably we need to
handle the SFF rules directly and properly. Because we know the device
BAR 0-3 are not used in compatibility mode we load them with the values
that are implied (and indeed which many controllers actually
thoughtfully put there in this mode anyway).

This removes special cases in the IDE layer and libata which now knows
that bar 0/1/2/3 always contain the correct address. It means our
resource allocation map is accurate from boot, not "mostly accurate"
after ide is loaded, and it shoots lots of code. There is also lots more
code and magic constant knowledge to shoot once this is in and settled.

Been in my test tree for a while both with drivers/ide and with libata.
Wants some -mm shakedown in case I've missed something dumb or there are
corner cases lurking.
Signed-off-by: default avatarAlan Cox <alan@redhat.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
      368c73d4
    • Stephen Hemminger's avatar
      PCI: save/restore PCI-X state · cc692a5f
      Stephen Hemminger authored 
      Shouldn't PCI-X state be saved/restored?  No device really needs this
right now. qla24xx (fc HBA) and mthca (infiniband) don't do suspend, 
and sky2 resets its tweaks when links are brought up.
Signed-off-by: default avatarStephen Hemminger <shemminger@osdl.org>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
      cc692a5f
    • Michael Ellerman's avatar
      PCI: Make some MSI-X #defines generic · e65e5fb5
      Michael Ellerman authored 
      Move some MSI-X #defines into pci_regs.h so they can be used
outside of drivers/pci.
Signed-off-by: default avatarMichael Ellerman <michael@ellerman.id.au>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
      e65e5fb5
    • Greg Kroah-Hartman's avatar
      PCI: Let PCI_MULTITHREAD_PROBE not be broken · 009af1ff
      Greg Kroah-Hartman authored 
      It's not really broken, but people keep running into other problems
caused by it.  Re-enable it so that the drivers get stress tested.
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
      009af1ff
  3. 29 Nov, 2006 22 commits
  5. 28 Nov, 2006 7 commits
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