- 05 May, 2016 40 commits
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Flora Cui authored
Signed-off-by:
Flora Cui <Flora.Cui@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Reviewed-by:
Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by:
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Flora Cui authored
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Flora Cui authored
46c34bcb6a15dd85329a39a5e72c62108626acdc put all block’s clockgating support in SMC. The sequence in suspend routine should be adjusted accordingly, otherwise it causes asic hang. Signed-off-by:
Eric Huang <JinHuiEric.Huang@amd.com> Signed-off-by:
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Eric Huang authored
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Eric Huang authored
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Flora Cui authored
This is to workaround regression introduced in 46c34bcb6a15dd85329a39a5e72c62108626acdc. It should be reverted with a final fix. Signed-off-by:
Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
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Eric Huang authored
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Christian König <christian.koenig@amd.com> Signed-off-by:
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Eric Huang authored
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Eric Huang authored
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Eric Huang authored
Needed for per CU powergating. Reviewed-by:
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Eric Huang authored
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Eric Huang authored
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yanyang1 authored
sync the code form catalyst CL:#1230866. Signed-off-by:
yanyang1 <Young.Yang@amd.com> Reviewed-by:
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yanyang1 authored
update relational h files. Signed-off-by:
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yanyang1 authored
add CGS_UCODE_ID_SMU_SK. Signed-off-by:
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Eric Huang authored
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Eric Huang authored
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Rex Zhu authored
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Rex Zhu authored
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Rex Zhu authored
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rezhu authored
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rezhu authored
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Sonny Jiang authored
Ellesmere and Baffin are VCE 3.4 Signed-off-by:
Sonny Jiang <sonny.jiang@amd.com> Reviewed-by:
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Sonny Jiang authored
Ellesmere and Baffin are UVD 6.3 Signed-off-by:
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Flora Cui authored
V2: use gfx_8_0_*.h instead of gfx_8_1_*.h v3: agd: integrate support for gfx info table Signed-off-by:
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Flora Cui authored
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Alex Deucher authored
Fetch the values from atom rather than hardcoding them in the driver. Signed-off-by: -
Flora Cui authored
V2: seperate baffin & ellesmere settings instead of using fiji ones. Signed-off-by:
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Flora Cui authored
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Flora Cui authored
V2: add golden_settings_baffin_a11 instead of reuse golden_settings_fiji_a10 Signed-off-by:
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Alex Deucher authored
Setup the disp clock and dp reference clock. This is now a separate command table on elm/baf compared to older asics. Reviewed-by:
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Alex Deucher authored
SetPixelClock table handles pll divider calculation and spread spectrum setup, so no need to use calculate the dividers and call the ss enable cmd table. Reviewed-by:
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Alex Deucher authored
New PLL scheme on ELM/BAF. v2: squash in pll fix. Plls are part of the phys. Reviewed-by:
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Alex Deucher authored
New uniphy transmitter setup table for elm/baf. Reviewed-by:
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Alex Deucher authored
New digital encoder setup table for elm/baf. Reviewed-by:
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Alex Deucher authored
New version of the SetPixelClock table for elm/baf. The new table calculates the pll dividers and handles spread spectrum calculations and setup. Reviewed-by:
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Alex Deucher authored
New cmd table for ELM/BAF for setting the dispclock or dprefclock. Signed-off-by:
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Alex Deucher authored
update to internal version 893 v2: Pull in gfx_info changes from 898 Reviewed-by:
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Alex Deucher authored
Fixes array overflow on these chips. Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Alex Deucher authored
Prerequiste for the next patch which ups the limits. Reviewed-by:
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