1. 10 Jul, 2011 2 commits
    • Santosh Shilimkar's avatar
      OMAP4: powerdomain data: Remove unsupported MPU powerdomain state · a57341f7
      Santosh Shilimkar authored
      On OMAP4430 devices, because of boot ROM code bug, MPU OFF state can't
      be attempted independently. When coming out of MPU OFF state, ROM code
      disables the clocks of IVAHD, TESLA which is not desirable. Hence the
      MPU OFF state is not usable on OMAP4430 devices.
      
      OMAP4460 onwards, MPU OFF state will be descoped completely because
      the DDR firewall falls in MPU power domain. When the MPU hit OFF state,
      DDR won't be accessible for other initiators. The deepest state supported
      is open switch retention (OSWR) just like CORE and PER PD on OMAP4430.
      
      So in summary MPU power domain OFF state is not supported on OMAP4
      and onwards designs. Thanks to new PRCM design, device off mode can
      still be achieved with power domains hitting OSWR state.
      Signed-off-by: default avatarSantosh Shilimkar <santosh.shilimkar@ti.com>
      Signed-off-by: default avatarRajendra Nayak <rnayak@ti.com>
      [b-cousson@ti.com: Fix changelog typos]
      Signed-off-by: default avatarBenoit Cousson <b-cousson@ti.com>
      Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
      a57341f7
    • Santosh Shilimkar's avatar
      OMAP4: clock data: Keep GPMC clocks always enabled and hardware managed · 93cac2ad
      Santosh Shilimkar authored
      On OMAP4, CPU accesses on unmapped addresses are redirected to GPMC by
      L3 interconnect. Because of CPU speculative nature, such accesses are
      possible which can lead to indirect access to GPMC and if it's clock is
      not running, it can result in hang/abort on the platform.
      
      Above makes access to GPMC unpredictable during the execution, so it's
      module mode needs to be kept under hardware control instead of software
      control.
      Since the auto gating is supported for GPMC, there isn't any power impact
      because of this change.
      
      The issue was un-covered with security middleware running along with HLOS.
      In this case GPMC had a valid MMU descriptor on secure side where as HLOS
      didn't map the GMPC because it isn't being used.
      Signed-off-by: default avatarSantosh Shilimkar <santosh.shilimkar@ti.com>
      [b-cousson@ti.com: Update subject and fix typos in the changelog]
      Signed-off-by: default avatarBenoit Cousson <b-cousson@ti.com>
      Cc: Kevin Hilman <khilman@ti.com>
      Cc: Rajendra Nayak <rnayak@ti.com>
      Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
      93cac2ad
  2. 13 Jun, 2011 10 commits
  3. 12 Jun, 2011 8 commits
  4. 11 Jun, 2011 16 commits
  5. 10 Jun, 2011 4 commits