- 16 May, 2016 3 commits
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Muhammad Falak R Wani authored
It is preferred to use ARRAY_SIZE() for size calculation, instead using sizeof(array)/sizeof(*array). It makes the code more readable. Reviewed-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Eric Engestrom <eric.engestrom@imgtec.com> Signed-off-by:
Muhammad Falak R Wani <falakreyaz@gmail.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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tom will authored
When the initial value of i is greater than zero, it may cause endless loop, resulting in array out of bounds, fix it. This is a port of the radeon fix to amdgpu. Signed-off-by:
tom will <os@iscas.ac.cn> Signed-off-by:
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tom will authored
When the initial value of i is greater than zero, it may cause endless loop, resulting in array out of bounds, fix it. Signed-off-by:
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- 13 May, 2016 6 commits
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Eric Huang authored
Update sclk smc table rather than mclk smc table for sclk updates. Reviewed-by:
Eric Huang <JinHuiEric.Huang@amd.com> Signed-off-by:
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Eric Huang authored
Update sclk smc table rather than mclk smc table for sclk updates. Reviewed-by:
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Rex Zhu authored
This avoids problems with multiple GPUs. For example, if the first GPU failed before amdgpu_fence_init() was called, amdgpu_fence_slab_ref is still 0 and it will get decremented in amdgpu_fence_driver_fini(). This will lead to a crash during init of the second GPU since amdgpu_fence_slab_ref is not 0. v2: add functions for init/exit instead of moving the variables into the driver. Signed-off-by:Rex Zhu <Rex.Zhu@amd.com> Reviewed-by:
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Rex Zhu authored
It's generic and used by multiple asics. Signed-off-by:
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Rex Zhu authored
&& was used instead of || Signed-off-by:
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Rex Zhu authored
SMC uses CurrSclkPllRange structure to keep track of what range of PLL SCLK is sitting on. Driver overwrites this value to 0 because it's part of DPM table and driver doesn't program this. This change will set this field to 0xFF every time there's a init SMC table call. Signed-off-by:
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- 11 May, 2016 31 commits
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Harish Kasiviswanathan authored
Bundle some VM table parameters into amdgpu_vm_update_params structure, so that number of function parameters can be reduced. Only structural change, no logic change. v2: agd: squash in fix from Harish Signed-off-by:
Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Reviewed-by:
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Marek Olšák authored
TC_WB_ACTION must be set according to the docs Signed-off-by:
Marek Olšák <marek.olsak@amd.com> Reviewed-by:
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Huang Rui authored
Actually, pp_sw_init executes pptable_init and backend_init orderly if they are initialized successfully. So rewrite it to make code more readable. Reviewed-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Alex Deucher authored
Missing offset in the audio offset array. Reported-by:
Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by:
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Christian König authored
We leaked the BO in the error pass, additional to that we only have one user fence for all IBs in a job. v2: remove white space changes Signed-off-by:
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Christian König authored
They are the same for all IBs. Signed-off-by:
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Christian König authored
We only have one context for all IBs. Signed-off-by:
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Christian König authored
It was a source of bugs to repeat that in each IP version. v2: rename parameter Signed-off-by:
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Christian König authored
This fixes the handling which was completely broken when you ad more than one preamble IB. Signed-off-by:
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Chunming Zhou authored
Need to wait on the fence as well. Signed-off-by:
Chunming Zhou <David1.Zhou@amd.com> Reviewed-by:
Monk Liu <monk.liu@amd.com> Signed-off-by:
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Sonny Jiang authored
Updated to handle latest UVD ucode. Signed-off-by:
Sonny Jiang <sonny.jiang@amd.com> Reviewed-by:
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Christian König authored
Use of the ctx pointer is not safe, because they are likely already be assigned to another ctx when doing comparing. v2: recreate from scratch, avoid all unnecessary changes. Signed-off-by:
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Tom St Denis authored
Signed-off-by:
Tom St Denis <tom.stdenis@amd.com> Reviewed-by:
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Tom St Denis authored
Add name that we can print out in kernel messages to aid in debugging. v2: drop DAL changes for upstream Signed-off-by:
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Alex Deucher authored
When this flag is set, we program the hardware to execute the flip during horizontal blank (i.e. for the next scanline) instead of during vertical blank (i.e. for the next frame). Ported from radeon commit: drm/radeon: Support DRM_MODE_PAGE_FLIP_ASYNC v2: drop DAL change for upstream Reviewed-by:
Michel Dänzer <michel.daenzer@amd.com> Signed-off-by:
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Alex Deucher authored
They are part of the phy so you can't share them. Signed-off-by: -
Nils Wallménius authored
Signed-off-by:
Nils Wallménius <nils.wallmenius@gmail.com> Signed-off-by:
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Nils Wallménius authored
a / (1 << b) is equivalent to a >> b for unsigned values Signed-off-by:
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Nils Wallménius authored
Signed-off-by:
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Nils Wallménius authored
Replacing magic numbers in calculation of sleep divider id for fiji and polaris. Signed-off-by:
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Alex Deucher authored
Noticed by n1s on IRC. Signed-off-by: -
Alex Deucher authored
Fetch this info once at init and just store the results for future requests. Reviewed-by:
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Christian König authored
This is the result of running the following commands: find drivers/gpu/drm/amd/ -name "*.h" -exec sed -i 's/[ \t]\+$//' {} \; find drivers/gpu/drm/amd/ -name "*.c" -exec sed -i 's/[ \t]\+$//' {} \; find drivers/gpu/drm/amd/ -name "*.h" -exec sed -i 's/ \+\t/\t/' {} \; find drivers/gpu/drm/amd/ -name "*.c" -exec sed -i 's/ \+\t/\t/' {} \; v2: drop changes to DAL and internal headers Signed-off-by: -
Christian König authored
Just set it to zero instead. Signed-off-by:
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Christian König authored
The client ID is now unique, so no need to resert the owner fields any more. v2: remove unused variables as well Signed-off-by:
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Christian König authored
Otherwise we could (in theory) run into problems on 32bit systems. Signed-off-by:
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Christian König authored
Signed-off-by:
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Monk Liu authored
This fixes Tonga vm-fault issue when running disaster (a multiple context GL heavy tests), We should always flush & invalidate hdp no matter vm used or not. Signed-off-by:
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Tom St Denis authored
Tested via vdpau/mpv. Signed-off-by:
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Chunming Zhou authored
hardware ring is async processed, the job is executed in parallel. In some case, this will result vm fault, like jobs with different vmids. This works around a CPC hw issue which will eventually be fixed in fw. Signed-off-by:
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Monk Liu authored
ib.vm is a legacy way to get vm, after scheduler implemented vm should be get from job, and all ibs from one job share the same vm, no need to keep ib.vm just move vm field to job. this patch as well add job as paramter to ib_schedule so it can get vm from job->vm. v2: agd: sqaush in: drm/amdgpu: check if ring emit_vm_flush exists in vm flush No vm flush on engines that don't support VM. bug: https://bugs.freedesktop.org/show_bug.cgi?id=95195Signed-off-by:
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