- 11 May, 2017 2 commits
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Boris Brezillon authored
NAND branches are now hosted on MTD repos, nand/next is on l2-mtd and nand/fixes will be on linux-mtd. Signed-off-by:
Boris Brezillon <boris.brezillon@free-electrons.com> [Brian: added branch names] Signed-off-by:
Brian Norris <computersforpeace@gmail.com>
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Christophe Leroy authored
This patch updates the binding documentation in accordance with commit 44dd1828 ("mtd: nand: gpio: make nCE GPIO optional") Signed-off-by:
Christophe Leroy <christophe.leroy@c-s.fr> Reported-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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- 03 May, 2017 1 commit
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Alexander Couzens authored
The old 1-bit hamming layout requires ECC data to be placed at a fixed offset, and not necessarily at the end of the OOB area. Add this old layout back in order to fix legacy setups. Fixes: 41b207a7 ("mtd: nand: implement the default mtd_ooblayout_ops") Cc: <stable@vger.kernel.org> Signed-off-by:
Alexander Couzens <lynxis@fe80.eu> Acked-by:
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- 02 May, 2017 3 commits
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Dan Carpenter authored
We only need to allocate sizeof(struct oxnas_nand_ctrl) which is 192 bytes and not sizeof(struct nand_chip) which is a much larger 3056 bytes. Fixes: 66859249 ("mtd: nand: Add OX820 NAND Support") Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Acked-by:
Neil Armstrong <narmstrong@baylibre.com> Acked-by:
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Ludovic Barre authored
This patch adds documentation of device tree bindings for the STM32 QSPI controller. Signed-off-by:
Ludovic Barre <ludovic.barre@st.com> Acked-by:
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git://github.com/spi-nor/linuxBrian Norris authored
From Cyrille: """ This pull request contains the following notable changes: - fixes in the hisi SPI controller driver. - fixes in the intel SPI controller driver. - fixes in the Mediatek SPI controller driver. - fixes to some SPI flash memories not supported the Chip Erase command. - add support to some new memory parts (Winbond, Macronix, Micron, ESMT). - add new driver for the STM32 QSPI controller. """
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- 01 May, 2017 3 commits
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Brian Norris authored
From Boris: """ This pull request contains: - some minor fixes/improvements on existing drivers (fsmc, gpio, ifc, davinci, brcmnand, omap) - a huge cleanup/rework of the denali driver accompanied with core fixes/improvements to simplify the driver code - a complete rewrite of the atmel driver to support new DT bindings make future evolution easier - the addition of per-vendor detection/initialization steps to avoid extending the nand_ids table with more extended-id entries """
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Guochun Mao authored
When nor's size larger than 16MByte, nor's address width maybe set to 3 or 4, and controller should change address width according to nor's setting. Signed-off-by:
Guochun Mao <guochun.mao@mediatek.com> Signed-off-by:
Cyrille Pitchen <cyrille.pitchen@atmel.com>
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Ludovic Barre authored
The quadspi is a specialized communication interface targeting single, dual or quad SPI Flash memories. It can operate in any of the following modes: -indirect mode: all the operations are performed using the quadspi registers -read memory-mapped mode: the external Flash memory is mapped to the microcontroller address space and is seen by the system as if it was an internal memory Signed-off-by:
Marek Vasut <marek.vasut@gmail.com> Signed-off-by:
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- 25 Apr, 2017 21 commits
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Kamal Dasu authored
On brcmnand controller v6.x and v7.x, the #WP pin is controlled through the NAND_WP bit in CS_SELECT register. The driver currently assumes that toggling the #WP pin is instantaneously enabling/disabling write-protection, but it actually takes some time to propagate the new state to the internal NAND chip logic. This behavior is sometime causing data corruptions when an erase/program operation is executed before write-protection has really been disabled. Fixes: 27c5b17c ("mtd: nand: add NAND driver "library" for Broadcom STB NAND controller") Signed-off-by:
Kamal Dasu <kdasu.kdev@gmail.com> Signed-off-by:
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Sekhar Nori authored
Add a comment clarifying that NAND subpage write on keystone works, but is not being enabled in the interest of backward compatibility. Signed-off-by:
Sekhar Nori <nsekhar@ti.com> Signed-off-by:
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Roger Quadros authored
commit c9711ec5 ("mtd: nand: omap: Clean up device tree support") caused the parent device name to be changed from "omap2-nand.0" to "<base address>.nand" (e.g. 30000000.nand on omap3 platforms). This caused mtd->name to be changed as well. This breaks partition creation via mtdparts passed by u-boot as it uses "omap2-nand.0" for the mtd-id. Fix this by explicitly setting the mtd->name to "omap2-nand.<CS number>" if it isn't already set by nand_set_flash_node(). CS number is the NAND controller instance ID. Fixes: c9711ec5 ("mtd: nand: omap: Clean up device tree support") Cc: <stable@vger.kernel.org> # 4.7+ Reported-by:
Leto Enrico <enrico.leto@siemens.com> Reported-by:
Adam Ford <aford173@gmail.com> Suggested-by:
Roger Quadros <rogerq@ti.com> Signed-off-by:
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Christophe Jaillet authored
of_device_id tables should be NULL terminated. Fixes: 07b23e3db9ed ("mtd: nand: Cleanup/rework the atmel_nand driver") Signed-off-by:Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by:
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Dan Carpenter authored
We accidentally return 1 on error instead of proper error codes. Fixes: 07b23e3db9ed ("mtd: nand: Cleanup/rework the atmel_nand driver") Signed-off-by: -
Masahiro Yamada authored
In some cases, nand_do_{read,write}_ops is passed with unaligned ops->datbuf. Drivers using DMA will be unhappy about unaligned buffer. The new struct member, buf_align, represents the minimum alignment the driver require for the buffer. If the buffer passed from the upper MTD layer does not have enough alignment, nand_do_*_ops will use bufpoi. Signed-off-by:Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by:
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Masahiro Yamada authored
Some NAND controllers are using DMA engine requiring a specific buffer alignment. The core provides no guarantee on the nand_buffers pointers, which forces some drivers to allocate their own buffers and pass the NAND_OWN_BUFFERS flag. Rework the nand_buffers allocation logic to allocate each buffer independently. This should make most NAND controllers/DMA engine happy, and allow us to get rid of these custom buf allocation in NAND controller drivers. Signed-off-by:
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Masahiro Yamada authored
Commit 271707b1 ("mtd: nand: denali: max_banks calculation changed in revision 5.1") added a revision check to support the new max_banks encoding. Its git-log states "The encoding of max_banks changed in Denali revision 5.1". There are exceptional cases, for example, the revision register on some UniPhier SoCs says the IP is 5.0 but the max_banks is encoded in the new format. This IP updates the resister specification from time to time (often breaking the backward compatibility), but the revision number is not incremented correctly. The max_banks is not only the case that needs revision checking. Let's allow to override an incorrect revision number. Signed-off-by:
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Masahiro Yamada authored
"pdev" is much more often used to point a platform_device, so this will help the driver code look consistent across the kernel. While we are here, fix "line over 80 characters" coding style violations. Signed-off-by:
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Masahiro Yamada authored
The driver sets appropriate DMA mask. Delete the "dma-mask" DT property. See [1] for negative comments for this binding. [1] https://lkml.org/lkml/2016/2/8/57Signed-off-by:
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Masahiro Yamada authored
The current driver only supports the DMA engine up to 32 bit physical address, but there also exists 64 bit capable DMA engine for this IP. The data DMA setup sequence is completely different, so I added the 64 bit DMA code as a new function denali_setup_dma64(). The 32 bit one has been renamed to denali_setup_dma32(). Signed-off-by:
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Masahiro Yamada authored
There are various customizable parameters, so several variants for this IP. A generic compatible like "denali,denali-nand-dt" is useless. Moreover, there are multiple things wrong with this string. (Refer to Rob's comment [1]) The "denali,denali-nand-dt" was added by Altera for the SOCFPGA port. Replace it with a more specific string "altr,socfpga-denali-nand". There are no users (in upstream) of the old compatible string. The Denali IP on SOCFPGA incorporates the hardware ECC fixup engine. So, this capability should be associated with the compatible. [1] https://lkml.org/lkml/2016/12/1/450Signed-off-by:
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Masahiro Yamada authored
Some old versions of the Denali IP (perhaps used only for Intel?) detects ECC errors and provides correct data via a register, but does not touch the transferred data. So, the software must fixup the data in the buffer according to the provided ECC correction information. Newer versions perform ECC correction before transferring the data. No more software intervention is needed. The ECC_ERROR_ADDRESS and ECC_CORRECTION_INFO registers were deprecated. Instead, the number of corrected bit-flips are reported via the ECC_COR_INFO register. When an uncorrectable ECC error happens, a status flag is set to the INTR_STATUS and ECC_COR_INFO registers. As is often the case with this IP, the register view of INTR_STATUS had broken compatibility. For older versions (SW ECC fixup): bit 0: ECC_TRANSACTION_DONE bit 1: ECC_ERR For newer versions (HW ECC fixup): bit 0: ECC_UNCOR_ERR bit 1: Reserved Due to this difference, the irq_mask must be fixed too. The existing handle_ecc() has been renamed to denali_sw_ecc_fixup() for clarification. What is unfortunate with this feature is we can not know the total number of corrected/uncorrected errors in a page. The register ECC_COR_INFO reports the maximum of per-sector bitflips. This is useful for ->read_page return value, but ecc_stats.{corrected,failed} increments may not be precise. Signed-off-by: -
Masahiro Yamada authored
This part is wrong in multiple ways: [1] is_erased() is called against "buf" twice, so the OOB area is not checked at all. The second call should check chip->oob_poi. [2] This code block is nested by double "if (check_erase_page)". The inner one is redundant. [3] The ECC_ERROR_ADDRESS register reports which sector(s) had uncorrectable ECC errors. It is pointless to check the whole page if only one sector contains errors. [4] Unfortunately, the Denali ECC correction engine has already manipulated the data buffer before it decides the bitflips are uncorrectable. That is, not all of the data are 0xFF after an erased page is processed by the ECC engine. The current is_erased() helper could report false-positive ECC errors. Actually, a certain mount of bitflips are allowed in an erased page. The core framework provides nand_check_erased_ecc_chunk() that takes the threshold into account. Let's use this. This commit reworks the code to solve those problems. Please note the erased page checking is implemented as a separate helper function instead of embedding it in the loop in handle_ecc(). The reason is that OOB data are needed for the erased page checking, but the controller can not start a new transaction until all ECC error information is read out from the registers. Signed-off-by:
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Masahiro Yamada authored
This function is wrong in multiple ways: [1] Counting corrected bytes instead of corrected bits. The following code is counting the number of corrected _bytes_. /* correct the ECC error */ buf[offset] ^= err_cor_value; mtd->ecc_stats.corrected++; bitflips++; What the core framework expects is the number of corrected _bits_. They can be different if multiple bitflips occur within one byte. [2] total number of errors instead of max of per-sector errors The core framework expects that corrected errors are counted per sector, then the max value should be taken. The current code simply iterates over the whole page, i.e. counts the total number of correction in the page. This means "too many bitflips" is triggered earlier than it should be, i.e. the NAND device is worn out sooner. Besides those bugs, this function is unreadable due to the deep nesting. Notice the whole code in this function is wrapped in if (irq_status & INTR__ECC_ERR), so this conditional can be moved out of the function. Also, use shorter names for local variables. Re-work the function to fix all the issues. Signed-off-by: -
Masahiro Yamada authored
The pipeline read-ahead function of the Denali IP enables continuous reading from the device; while data is being read out by a CPU, the controller maintains additional commands for streaming data from the device. This will reduce the latency of the second page or later. This feature is obviously no help for per-page accessors of Linux NAND driver interface. In the current implementation, the pipeline command is issued to load a single page, then data are read out immediately. The use of the pipeline operation is not adding any advantage, but just adding complexity to the code. Remove. Signed-off-by:
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Masahiro Yamada authored
Commit 28309572 ("mtd: name the mtd device with an optional label property") allow us to identify a chip in a user-friendly way. If nand_set_flash_node() picks up the "label" from DT, let's respect it. Otherwise, let it fallback to the current name "denali-nand". Signed-off-by:
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Masahiro Yamada authored
The comment for ecc.read_page() requires that it should return "0 if bitflips uncorrectable". Actually, drivers could return positive values when uncorrectable bitflips occur. For example, nand_read_page_swecc() is the case. If ecc.correct() returns -EBADMSG for the first ECC sector, and a positive value for the second one, nand_read_page_swecc() returns a positive max_bitflips and increments ecc_stats.failed for the same page. The requirement can be relaxed by tweaking nand_do_read_ops(). Move the max_bitflips calculation below the retry. Signed-off-by:
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Boris Brezillon authored
The last/only user of the chip->write_page() hook (the Atmel NAND controller driver) has been reworked and is no longer specifying a custom ->write_page() implementation. Drop this hook before someone else start abusing it. Signed-off-by:
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Boris Brezillon authored
The old NAND bindings were not exactly describing the hardware topology and were preventing definitions of several NAND chips under the same NAND controller. New bindings address these limitations and should be preferred over the old ones for new SoCs/boards. Old bindings are still supported for backward compatibility but are marked deprecated in the doc. Signed-off-by:
Nicolas Ferre <nicolas.ferre@microchip.com> Acked-by:
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Boris Brezillon authored
This is a complete rewrite of the driver whose main purpose is to support the new DT representation where the NAND controller node is now really visible in the DT and appears under the EBI bus. With this new representation, we can add other devices under the EBI bus without risking pinmuxing conflicts (the NAND controller is under the EBI bus logic and as such, share some of its pins with other devices connected on this bus). Even though the goal of this rework was not necessarily to add new features, the new driver has been designed with this in mind. With a clearer separation between the different blocks and different IP revisions, adding new functionalities should be easier (we already have plans to support SMC timing configuration so that we no longer have to rely on the configuration done by the bootloader/bootstrap). Also note that we no longer have a custom ->cmdfunc() implementation, which means we can now benefit from new features added in the core implementation for free (support for new NAND operations for example). The last thing that we gain with this rework is support for multi-chips and multi-dies chips, thanks to the clean NAND controller <-> NAND devices representation. During this transition we also dropped support for AVR32 SoCs which should soon disappear from mainline (removal of the AVR32 arch is planned for 4.12). This new driver has been tested on several platforms (at91sam9261, at91sam9g45, at91sam9x5, sama5d3 and sama5d4) to make sure it did not introduce regressions, and it's worth mentioning that old bindings are still supported (which partly explain the positive diffstat). Signed-off-by:
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- 19 Apr, 2017 7 commits
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Rafał Miłecki authored
OF core code provides helpers for counting strings and reading them so use them instead of doing this manually. This simplifies the code a bit. Signed-off-by:
Rafał Miłecki <rafal@milecki.pl> Reviewed-by:
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Cyrille Pitchen authored
Switch to my alternative address as primary address. Signed-off-by:
Cyrille Pitchen <cyrille.pitchen@wedev4u.fr> Signed-off-by:
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Geliang Tang authored
Since macros MTDSWAP_ECNT_MIN() and MTDSWAP_ECNT_MAX() have been defined in mtdswap.c, use them instead of open-coding. Signed-off-by:
Geliang Tang <geliangtang@gmail.com> Acked-by:
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Joe Perches authored
To enable eventual removal of pr_warning This makes pr_warn use consistent for drivers/mtd Prior to this patch, there were 7 uses of pr_warning and 31 uses of pr_warn in drivers/mtd Signed-off-by:
Joe Perches <joe@perches.com> Signed-off-by:
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Linus Walleij authored
The current way of building the of_physmap add-ons result in just the add-on being in the object code, and not the actual core implementation and regress the Gemini and Versatile. Bake the physmap_of.o object by baking physmap_of_core.o and adding the Versatile and/or Gemini add-ons to the final object. Rename the source file physmap_of_core.c to get the desired build components. Suggested-by:
Linus Walleij <linus.walleij@linaro.org> Acked-by:
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Rafał Miłecki authored
This allows better compile-time optimizations with CONFIG_OF disabled. Signed-off-by:
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Colin Ian King authored
trivial fix to spelling mistake in JFFS2_ERROR message Signed-off-by:
Colin Ian King <colin.king@canonical.com> [Brian: also fix 'an' -> 'a'] Signed-off-by:
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- 16 Apr, 2017 1 commit
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Mathias Kresin authored
All required stateless 4-byte op codes are supported by this flash chip. The stateless 4-byte support can't be autodetected due to a missing 4-byte Address Instruction Table in SFDP. Fixes hangs on reboot for SoCs expecting the flash chip in 3byte mode. Signed-off-by:
Mathias Kresin <dev@kresin.me> Acked-by:
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- 10 Apr, 2017 1 commit
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Nobuhiro Iwamatsu authored
Add new Micron N25Q256A (N25Q256A11) 256Mbit NOR Flash in the list of supported devices. This chip has the same structure as the N25Q256A but ID and voltage (1V8) to use is different. Therefore, this adds N25Q256A11 as n25q256ax1. In the future, for new Micron memories we could use the patterns "n25q*ax1" for 1V8 and "n25q*ax3" for 3V3 memories. Signed-off-by:
Nobuhiro Iwamatsu <nobuhiro.iwamatsu.kw@hitachi.com> Signed-off-by:
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- 29 Mar, 2017 1 commit
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Simon Baatz authored
The clock gate used by orion_nand is not available on all platforms. When getting this optional clock gate, the code masked all errors. Let's be more precise here and actually only allow ENOENT. EPROBE_DEFER is handled like any other error code since probe deferral is not supported by drivers using module_platform_driver_probe(). Signed-off-by:
Simon Baatz <gmbnomis@gmail.com> Signed-off-by:
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