- 05 Aug, 2010 12 commits
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Chuanxiao Dong authored
Signed-off-by:
Chuanxiao Dong <chuanxiao.dong@intel.com> Signed-off-by:
David Woodhouse <David.Woodhouse@intel.com>
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Chuanxiao Dong authored
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Chuanxiao Dong authored
Signed-off-by:
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Chuanxiao Dong authored
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Chuanxiao authored
Hi, I have changed the outlook mail cliet to be linux mutt client and use my personal gmail to submit patches. Here are 5 new patches to fix nand/denali check patch errors. The other 4 patches will be sent out after this mail. Thanks for your review. >From d125ad3f57bbf517131dccad6b5933edf8c2632a Mon Sep 17 00:00:00 2001 From: Chuanxiao Dong <chuanxiao.dong@intel.com> Date: Tue, 3 Aug 2010 15:54:48 +0800 Subject: [PATCH 1/5] mtd: denali.c: clean up all whitespaces in code indent Signed-off-by:
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Barry Song authored
The IRQSTAT register is a W1C register used by the interrupt handler and may have its BUSY bit changed. This makes it somewhat unreliable for the polling devready function. So switch it over to use the BUSY bit in the STAT register that always reflects the current state of the hardware. This fixes driver hangs seen when the NAND flash is under heavy system load (like I/O benchmarks). Signed-off-by:
Barry Song <barry.song@analog.com> Signed-off-by:
Mike Frysinger <vapier@gentoo.org> Signed-off-by:
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Barry Song authored
Rather than forcing the platform resources to declare the desired page size, simply use the existing information passed down to us by the higher layers. This way we work out of the box with all flash chips that the kernel knows about. Signed-off-by:
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Barry Song authored
When resetting the ECC registers/counters, the bit will automatically clear itself once the reset has actually finished. So make sure we wait for that to occur before doing anything else rather than assuming everything is peachy and proceeding with stale ECC values. Signed-off-by:
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Barry Song authored
We used the platform rd_dly field when we meant to use the wr_dly field. Signed-off-by:
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Barry Song authored
The NAND base may send some controls which are neither CLE nor ALE, so we need to explicitly check both instead of assuming things are always one or the other. Otherwise, we sometimes send out illegal addresses to the NAND device. Signed-off-by:
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Barry Song authored
Our write_buf/read_buf funcs always do ECC in HW ECC mode. That is not needed for raw funcs. In fact, write_buf/read_buf should be a pure func for data input/output while chip->ecc.hwctl controls ECC. Unfortunately, we can't separate ECC from normal data input/output in our NFC, so our DMA write_buf/read_buf entries are coupled with ECC operations closely. Thus we need to provide dedicated read_page_raw/write_page_raw funcs where we do non-DMA transactions so as to avoid automatic ECC. Signed-off-by:
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Barry Song authored
The low level NAND driver doesn't care about filesystems, so punt the local comment indicating otherwise. Signed-off-by:
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- 04 Aug, 2010 9 commits
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Guillaume LECERF authored
Valid primary extension versions are: 1.0, 1.1, 1.2, 1.3 [1][2]. Fix the check in cfi_cmdset_0002 accordingly. [1] http://www.amd.com/us-en/assets/content_type/DownloadableAssets/cfi_r20.pdf, page 19 [2] http://www.amd.com/us-en/assets/content_type/DownloadableAssets/cfi_100_20011201.pdfSigned-off-by:
Florian Fainelli <florian@openwrt.org> Signed-off-by:
Guillaume LECERF <glecerf@gmail.com> Signed-off-by:
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Anton Vorontsov authored
spi_write_then_read() may return its own return codes (e.g. -EIO), so let's propagate the value down to the probe(). Also, remove jedec == 0 check, it isn't needed as nowadays we use dedicated SPI device IDs for non-JEDEC flashes. Suggested-by:
Barry Song <21cnbao@gmail.com> Signed-off-by:
Anton Vorontsov <avorontsov@mvista.com> Acked-by:
Artem Bityutskiy <Artem.Bityutskiy@nokia.com> Signed-off-by:
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Anton Vorontsov authored
Since commit 18c6182b ("Rework probing/JEDEC code"), m25p80 driver successfully registers chips even if JEDEC probing fails. This was needed to support non-JEDEC flashes. Though, it appears that some platforms (e.g. blackfin bf533 stamp[1]) used the old behavior to detect if there's any flash connected, so the driver have to fail on JEDEC probing errors. This patch restores the old behavior for JEDEC flashes, and adds "-nonjedec" SPI device IDs for M25Pxx flashes, so that the kernel still supports non-JEDEC flashes. [1] http://blackfin.uclinux.org/gf/project/uclinux-dist/tracker/?action=TrackerItemEdit&tracker_item_id=5975 Reported-by: Mingquan Pan Reported-by:
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Anatolij Gustschin authored
For no-mmu systems mmap() on RAM/ROM devices already works but for systems with mmu it probably was not tested and doesn't work. This patch allows using mmap() on MTD RAM/ROM devices on systems with MMU. It has been tested on mpc5121e based platform with MR0A16A MRAM device attached over LocalBus. Signed-off-by:
Anatolij Gustschin <agust@denx.de> Acked-by:
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Richard Cochran authored
This patch adds support for static flash partitioning from a platform device. Also, we clean up some weirdness where statements were separated by commas instead of semicolons. While we are at it, fix some minor bad white space, too. Signed-off-by:
Richard Cochran <richard.cochran@omicron.at> Signed-off-by:
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Eric Bénard authored
The mtd layer is responsible to call mtd->{suspend,resume}. Doing it again in the driver is wrong and results in a warning: nand_resume called for a chip which is not in suspended state at resume time. Removing the calls from the resume and suspend functions makes them empty allowing them to be deleted completely. Signed-off-by:Eric Bénard <eric@eukrea.com> Acked-by:
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by:
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Mark Ware authored
The variable 'syn' was being used uninitialized. Also fixed incorrect use of syn[] vs s[]. Tested on powerpc board with 64MiB DOC2000. Signed-off-by:
Mark Ware <mware@elphinstone.net> Signed-off-by:
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Kyungmin Park authored
Samsung SoCs use own chip_probe function. Don't touch the memory configuration at probe time. Signed-off-by:
Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by:
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Kyungmin Park authored
Samsung SoCs use the own OneNAND controler and detect OneNAND chip at power on. To use this feature, introduce the chip_probe function. Also remove workaround for Samsung SoCs. Signed-off-by:
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- 02 Aug, 2010 19 commits
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Rohit Hassan Sathyanarayan authored
Sending the patch for page address calculation based on device type. This resolves the OneNAND DDP device read problem as pointed by Enric. http://lists.infradead.org/pipermail/linux-mtd/2010-July/030920.htmlSigned-off-by:
Rohit HS <rohit.hs@samsung.com> Signed-off-by:
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Brian Norris authored
This is an update that depends on the previous patches I sent. We can now write to all the appropriate BB marker locations (i.e. pages 1 AND 2, bytes 1 AND 6) with nand_default_block_markbad() if necessary, according to the flags marked in chip->options. Note that I removed the line: ofs += mtd->oobsize; Unless I am wrong, this line was completely unnecessary in the first place. Signed-off-by:
Brian Norris <norris@broadcom.com> Signed-off-by:
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Dong, Chuanxiao authored
Fix all checkpatch.pl complaints. Artem: tweaked a little and fix tab indentations, so now this is not only about checkpatch, but also about making indentations look sane. Signed-off-by: -
Sudhakar Rajashekhara authored
On TI's DA830/OMAP-L137, DA850/OMAP-L138 and DM365, after setting the 4BITECC_ADD_CALC_START bit in the NAND Flash control register to 1 and before waiting for the NAND Flash status register to be equal to 1, 2 or 3, we have to wait till the ECC HW goes to correction state. Without this wait, ECC correction calculations will not be proper. This has been tested on DA830/OMAP-L137, DA850/OMAP-L138, DM355 and DM365 EVMs. Signed-off-by:
Sudhakar Rajashekhara <sudhakar.raj@ti.com> Acked-by:
Sneha Narnakaje <nsnehaprabha@ti.com> Signed-off-by:
Andrew Morton <akpm@linux-foundation.org> Signed-off-by:
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Brian Norris authored
This is a revision to PATCH 2/2 that I sent. Link: http://lists.infradead.org/pipermail/linux-mtd/2010-July/030911.html Added new flag for scanning of both bytes 1 and 6 of the OOB for a BB marker (instead of simply one or the other). The "check_pattern" and "check_short_pattern" functions were updated to include support for scanning the two different locations in the OOB. In order to handle increases in variety of necessary scanning patterns, I implemented dynamic memory allocation of nand_bbt_descr structs in new function 'nand_create_default_bbt_descr()'. This replaces some increasingly-unwieldy, statically-declared descriptors. It can replace several more (e.g. "flashbased" structs). However, I do not test the flashbased options personally. How this was tested: I referenced 30+ data sheets (covering 100+ parts), and I tested a selection of 10 different chips to varying degrees. Particularly, I tested the creation of bad-block descriptors and basic BB scanning on three parts: ST NAND04GW3B2D, 2K page ST NAND128W3A, 512B page Samsung K9F1G08U0A, 2K page To test these, I wrote some fake bad block markers to the flash (in OOB bytes 1, 6, and elsewhere) to see if the scanning routine would detect them properly. However, this method was somewhat limited because the driver I am using has some bugs in its OOB write functionality. Signed-off-by:
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Brian Norris authored
Some level of support for various scanning locations was already built in, but this required clean-up. First, BB marker location cannot be determined _only_ by the page size. Instead, I implemented some heuristic detection based on data sheets from various manufacturers (all found in nand_base.c:nand_get_flash_type()). Second, once these options were identified, they were not handled properly by nand_bbt.c:nand_default_bbt(). I updated the static nand_bbt_desc structs to reflect the need for more combinations of detection. The memory allocation here probably needs to be done dynamically in the very near future (see next patches). Signed-off-by:
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Conke Hu authored
Current driver prevents command-line partitions from being parsed when built-in partitions are defined in s3c2410_nand_set object, but it is not desirable in some cases. This patch tries to parse commad-line partitions prior to the built-in. Signed-off-by:
Conke Hu <conke@maxwit.com> Signed-off-by:
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Eric Bénard authored
* preset should be done before sending the reset command * without this, I get the following error on an i.MX35 : [ 0.900000] ------------[ cut here ]------------ [ 0.900000] WARNING: at kernel/irq/manage.c:290 __enable_irq+0x4c/0x88() [ 0.900000] Unbalanced enable for IRQ 33 [ 0.900000] Modules linked in: [ 0.900000] [<c002ffb8>] (unwind_backtrace+0x0/0xf0) from [<c02f7d0c>] (dump_stack+0x18/0x1c) [ 0.900000] [<c02f7d0c>] (dump_stack+0x18/0x1c) from [<c0049a44>] (warn_slowpath_common+0x54/0x6c) [ 0.900000] [<c0049a44>] (warn_slowpath_common+0x54/0x6c) from [<c0049b00>] (warn_slowpath_fmt+0x38/0x40) [ 0.900000] [<c0049b00>] (warn_slowpath_fmt+0x38/0x40) from [<c008f65c>] (__enable_irq+0x4c/0x88) [ 0.900000] [<c008f65c>] (__enable_irq+0x4c/0x88) from [<c008fca0>] (enable_irq+0x54/0x98) [ 0.900000] [<c008fca0>] (enable_irq+0x54/0x98) from [<c021e618>] (wait_op_done+0x40/0x134) [ 0.900000] [<c021e618>] (wait_op_done+0x40/0x134) from [<c021e808>] (send_cmd+0x30/0x38) [ 0.900000] [<c021e808>] (send_cmd+0x30/0x38) from [<c021eb8c>] (mxc_nand_command+0x26c/0x328) [ 0.900000] [<c021eb8c>] (mxc_nand_command+0x26c/0x328) from [<c021aa60>] (nand_scan_ident+0x188/0x6c0) [ 0.900000] [<c021aa60>] (nand_scan_ident+0x188/0x6c0) from [<c001a9cc>] (mxcnd_probe+0x2b8/0x3d0) [ 0.900000] [<c001a9cc>] (mxcnd_probe+0x2b8/0x3d0) from [<c01f9e88>] (platform_drv_probe+0x20/0x24) [ 0.900000] [<c01f9e88>] (platform_drv_probe+0x20/0x24) from [<c01f8c38>] (driver_probe_device+0xb0/0x164) [ 0.900000] [<c01f8c38>] (driver_probe_device+0xb0/0x164) from [<c01f8d54>] (__driver_attach+0x68/0x8c) [ 0.900000] [<c01f8d54>] (__driver_attach+0x68/0x8c) from [<c01f8348>] (bus_for_each_dev+0x50/0x84) [ 0.900000] [<c01f8348>] (bus_for_each_dev+0x50/0x84) from [<c01f8a9c>] (driver_attach+0x20/0x28) [ 0.900000] [<c01f8a9c>] (driver_attach+0x20/0x28) from [<c01f7c00>] (bus_add_driver+0x144/0x2dc) [ 0.900000] [<c01f7c00>] (bus_add_driver+0x144/0x2dc) from [<c01f906c>] (driver_register+0xb0/0x13c) [ 0.900000] [<c01f906c>] (driver_register+0xb0/0x13c) from [<c01fa13c>] (platform_driver_register+0x4c/0x60) [ 0.900000] [<c01fa13c>] (platform_driver_register+0x4c/0x60) from [<c01fa170>] (platform_driver_probe+0x20/0xa0) [ 0.900000] [<c01fa170>] (platform_driver_probe+0x20/0xa0) from [<c001a708>] (mxc_nd_init+0x18/0x24) [ 0.900000] [<c001a708>] (mxc_nd_init+0x18/0x24) from [<c002938c>] (do_one_initcall+0x64/0x1bc) [ 0.900000] [<c002938c>] (do_one_initcall+0x64/0x1bc) from [<c00084c4>] (kernel_init+0xe8/0x1ac) [ 0.900000] [<c00084c4>] (kernel_init+0xe8/0x1ac) from [<c002aee8>] (kernel_thread_exit+0x0/0x8) [ 0.900000] ---[ end trace 8bf72ac6ba089a19 ]--- [ 1.140000] NAND device: Manufacturer ID: 0x2c, Chip ID: 0xda (Micron NAND 256MiB 3,3V 8-bit) Signed-off-by:
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Roel Kluin authored
Signed-off-by:
Roel Kluin <roel.kluin@gmail.com> Signed-off-by:
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Kulikov Vasiliy authored
Remove unnesessary casts from void*. Signed-off-by:
Kulikov Vasiliy <segooon@gmail.com> Signed-off-by:
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Kulikov Vasiliy authored
Remove unnesessary casts from void*. Signed-off-by:
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Kulikov Vasiliy authored
Remove unnesessary casts from void*. Signed-off-by:
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Kulikov Vasiliy authored
Remove unnesessary casts from void*. Signed-off-by:
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Kulikov Vasiliy authored
Remove unnesessary casts from void*. Signed-off-by:
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Guillaume LECERF authored
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Brian Norris authored
NAND_BB_LAST_PAGE used to be in nand.h, but it pertained to bad block management and so belongs next to NAND_BBT_SCAN2NDPAGE in bbm.h. Also, its previous flag value (0x00000400) conflicted with NAND_BBT_SCANALLPAGES so I changed its value to 0x00008000. All uses of the name were modified to provide consistency with other "NAND_BBT_*" flags. Signed-off-by:
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Martin Krause authored
Test if a lock or unlock function is present (pointer not NULL) before calling it, to prevent a kernel dump. Artem: removed extra blank lines Signed-off-by:
Martin Krause <martin.krause@tqs.de> Signed-off-by:
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Brian Norris authored
Included the basic size info for NAND chips with ID of 0xAD or 0xD7. The first can be found in Hynix HY27SF161G2M, while the second can be found in Micron MT29F64G08 and the Samsung K9LBG08U0D (among others). Also, some 64 Gbit (or larger) chips identify as 0xD7 because they contain multiple smaller 32 Gbit chips. I assume it's safe to classify these under the 32 Gbit listing. Signed-off-by:
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Uwe Kleine-König authored
This fixes: drivers/mtd/nand/mxc_nand.c: In function 'mxcnd_resume': drivers/mtd/nand/mxc_nand.c:901: warning: unused variable 'host' Removing this variable was missed in 9c14b153. Signed-off-by:
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