1. 26 Jun, 2015 1 commit
    • Rodrigo Vivi's avatar
      drm/i915: Fix IPS related flicker · ac88cd73
      Rodrigo Vivi authored
      We cannot let IPS enabled with no plane on the pipe:
      
      BSpec: "IPS cannot be enabled until after at least one plane has
      been enabled for at least one vertical blank." and "IPS must be
      disabled while there is still at least one plane enabled on the
      same pipe as IPS." This restriction apply to HSW and BDW.
      
      However a shortcut path on update primary plane function
      to make primary plane invisible by setting DSPCTRL to 0
      was leting IPS enabled while there was no
      other plane enabled on the pipe causing flickerings that we were
      believing that it was caused by that other restriction where
      ips cannot be used when pixel rate is greater than 95% of cdclok.
      
      v2: Don't mess with Atomic path as pointed out by Ville.
      
      Reference: https://bugs.freedesktop.org/show_bug.cgi?id=85583
      Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
      Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
      Cc: stable@vger.kernel.org
      Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
      Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
      Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
      ac88cd73
  2. 22 Jun, 2015 1 commit
  3. 17 Jun, 2015 3 commits
  4. 15 Jun, 2015 4 commits
  5. 05 Jun, 2015 1 commit
  6. 29 May, 2015 3 commits
    • Michel Thierry's avatar
      drm/i915: limit PPGTT size to 2GB in 32-bit platforms · 501fd70f
      Michel Thierry authored
      We already set this limit for the GGTT.
      
      This is a temporary patch until a full replacement of size_t variables
      (inadequate in 32-bit kernel) is in place.
      
      Regression from:
      	commit a4e0bedc
      	Author: Michel Thierry <michel.thierry@intel.com>
      	Date:   Wed Apr 8 12:13:35 2015 +0100
      
      		drm/i915: Use complete address space in true PPGTT
      
      v2: Prettify code and explain why this is needed. (Chris)
      v3: Don't hide the compilation warning in 32-bit. (Chris)
      Suggested-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      Cc: Mika Kuoppala <mika.kuoppala@intel.com>
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Signed-off-by: default avatarMichel Thierry <michel.thierry@intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      501fd70f
    • Rodrigo Vivi's avatar
      drm/i915: Another fbdev hack to avoid PSR on fbcon. · d9a946b5
      Rodrigo Vivi authored
      With unified modeset and flip paths introduced recently when switching
      to fbcon PSR was being disabled on fb_set_par path but re-enabled on
      fb_pan_display one, causing missed screen updates and un unusable
      console.
      
      Regression introduced with:
      
      commit bb546623
      Author: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
      Date:   Tue Apr 21 17:13:13 2015 +0300
      
          drm/i915: Unify modeset and flip paths of intel_crtc_set_config()
      
      Cc: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
      Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      d9a946b5
    • Rodrigo Vivi's avatar
      drm/i915: Return the frontbuffer flip to enable intel_crtc_enable_planes. · 2d847d45
      Rodrigo Vivi authored
      Without this frontbuffer flip when enabling planes PSR got compromised
      and wasn't being enabled waiting forever on the flush that never
      arrived.
      
      Another solution would to create a enable_cursor function and split this
      frontbuffer flip among the different plane enable and disable functions.
      But if necessary this can be done in a follow up work. For now let's
      just fix the regression.
      
      It was removed by:
      
      commit 87d4300a
      Author: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
      Date:   Tue Apr 21 17:12:54 2015 +0300
      
          drm/i915: Move intel_(pre_disable/post_enable)_primary to intel_display.c, and use it there.
      
      Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
      Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      2d847d45
  7. 28 May, 2015 7 commits
  8. 27 May, 2015 1 commit
  9. 26 May, 2015 3 commits
  10. 22 May, 2015 7 commits
  11. 21 May, 2015 9 commits