1. 07 Apr, 2017 9 commits
  2. 06 Apr, 2017 1 commit
    • Radim Krčmář's avatar
      Merge tag 'kvm_mips_4.12_1' of git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/kvm-mips · 715958f9
      Radim Krčmář authored
      From: James Hogan <james.hogan@imgtec.com>
      
      KVM: MIPS: VZ support, Octeon III, and TLBR
      
      Add basic support for the MIPS Virtualization Module (generally known as
      MIPS VZ) in KVM. We primarily support the ImgTec P5600, P6600, I6400,
      and Cavium Octeon III cores so far. Support is included for the
      following VZ / guest hardware features:
      - MIPS32 and MIPS64, r5 (VZ requires r5 or later) and r6
      - TLBs with GuestID (IMG cores) or Root ASID Dealias (Octeon III)
      - Shared physical root/guest TLB (IMG cores)
      - FPU / MSA
      - Cop0 timer (up to 1GHz for now due to soft timer limit)
      - Segmentation control (EVA)
      - Hardware page table walker (HTW) both for root and guest TLB
      
      Also included is a proper implementation of the TLBR instruction for the
      trap & emulate MIPS KVM implementation.
      
      Preliminary MIPS architecture changes are applied directly with Ralf's
      ack.
      715958f9
  3. 29 Mar, 2017 17 commits
  4. 28 Mar, 2017 13 commits
    • James Hogan's avatar
      KVM: MIPS/Emulate: Properly implement TLBR for T&E · dc44abd6
      James Hogan authored
      Properly implement emulation of the TLBR instruction for Trap & Emulate.
      This instruction reads the TLB entry pointed at by the CP0_Index
      register into the other TLB registers, which may have the side effect of
      changing the current ASID. Therefore abstract the CP0_EntryHi and ASID
      changing code into a common function in the process.
      
      A comment indicated that Linux doesn't use TLBR, which is true during
      normal use, however dumping of the TLB does use it (for example with the
      relatively recent 'x' magic sysrq key), as does a wired TLB entries test
      case in my KVM tests.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Acked-by: default avatarRalf Baechle <ralf@linux-mips.org>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: "Radim Krčmář" <rkrcmar@redhat.com>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      dc44abd6
    • James Hogan's avatar
      MIPS: Allow KVM to be enabled on Octeon CPUs · 0ae3abcd
      James Hogan authored
      Octeon III has VZ ASE support, so allow KVM to be enabled on Octeon
      CPUs as it should now be functional.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: David Daney <david.daney@cavium.com>
      Cc: Andreas Herrmann <andreas.herrmann@caviumnetworks.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: "Radim Krčmář" <rkrcmar@redhat.com>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      0ae3abcd
    • James Hogan's avatar
      KVM: MIPS/VZ: Handle Octeon III guest.PRid register · 1f48f9be
      James Hogan authored
      Octeon III implements a read-only guest CP0_PRid register, so add cases
      to the KVM register access API for Octeon to ensure the correct value is
      read and writes are ignored.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: "Radim Krčmář" <rkrcmar@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: David Daney <david.daney@cavium.com>
      Cc: Andreas Herrmann <andreas.herrmann@caviumnetworks.com>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      1f48f9be
    • James Hogan's avatar
      KVM: MIPS/VZ: Emulate hit CACHE ops for Octeon III · 3ba731da
      James Hogan authored
      Octeon III doesn't implement the optional GuestCtl0.CG bit to allow
      guest mode to execute virtual address based CACHE instructions, so
      implement emulation of a few important ones specifically for Octeon III
      in response to a GPSI exception.
      
      Currently the main reason to perform these operations is for icache
      synchronisation, so they are implemented as a simple icache flush with
      local_flush_icache_range().
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: "Radim Krčmář" <rkrcmar@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: David Daney <david.daney@cavium.com>
      Cc: Andreas Herrmann <andreas.herrmann@caviumnetworks.com>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      3ba731da
    • James Hogan's avatar
      KVM: MIPS/VZ: VZ hardware setup for Octeon III · 824533ad
      James Hogan authored
      Set up hardware virtualisation on Octeon III cores, configuring guest
      interrupt routing and carving out half of the root TLB for guest use,
      restoring it back again afterwards.
      
      We need to be careful to inhibit TLB shutdown machine check exceptions
      while invalidating guest TLB entries, since TLB invalidation is not
      available so guest entries must be invalidated by setting them to unique
      unmapped addresses, which could conflict with mappings set by the guest
      or root if recently repartitioned.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: "Radim Krčmář" <rkrcmar@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: David Daney <david.daney@cavium.com>
      Cc: Andreas Herrmann <andreas.herrmann@caviumnetworks.com>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      824533ad
    • James Hogan's avatar
      KVM: MIPS/T&E: Report correct dcache line size · 867f4da7
      James Hogan authored
      Octeon CPUs don't report the correct dcache line size in CP0_Config1.DL,
      so encode the correct value for the guest CP0_Config1.DL based on
      cpu_dcache_line_size().
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: "Radim Krčmář" <rkrcmar@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: David Daney <david.daney@cavium.com>
      Cc: Andreas Herrmann <andreas.herrmann@caviumnetworks.com>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      867f4da7
    • James Hogan's avatar
      KVM: MIPS/TLB: Handle virtually tagged icaches · 1c506c9c
      James Hogan authored
      When TLB entries are invalidated in the presence of a virtually tagged
      icache, such as that found on Octeon CPUs, flush the icache so that we
      don't get a reserved instruction exception even though the TLB mapping
      is removed.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: "Radim Krčmář" <rkrcmar@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: David Daney <david.daney@cavium.com>
      Cc: Andreas Herrmann <andreas.herrmann@caviumnetworks.com>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      1c506c9c
    • James Hogan's avatar
      KVM: MIPS/Emulate: Adapt T&E CACHE emulation for Octeon · 4fa9de5a
      James Hogan authored
      Cache management is implemented separately for Cavium Octeon CPUs, so
      r4k_blast_[id]cache aren't available. Instead for Octeon perform a local
      icache flush using local_flush_icache_range(), and for other platforms
      which don't use c-r4k.c use __flush_cache_all() / flush_icache_all().
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: "Radim Krčmář" <rkrcmar@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: David Daney <david.daney@cavium.com>
      Cc: Andreas Herrmann <andreas.herrmann@caviumnetworks.com>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      4fa9de5a
    • James Hogan's avatar
      MIPS: Add Octeon III register accessors & definitions · 7d8a528d
      James Hogan authored
      Add accessors for some VZ related Cavium Octeon III specific COP0
      registers, along with field definitions. These will mostly be used by
      KVM to set up interrupt routing and partition the TLB between root and
      guest.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Acked-by: default avatarRalf Baechle <ralf@linux-mips.org>
      Cc: David Daney <david.daney@cavium.com>
      Cc: Andreas Herrmann <andreas.herrmann@caviumnetworks.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: "Radim Krčmář" <rkrcmar@redhat.com>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      7d8a528d
    • James Hogan's avatar
      KVM: MIPS/VZ: Trace guest mode changes · edec9d7b
      James Hogan authored
      Create a trace event for guest mode changes, and enable VZ's
      GuestCtl0.MC bit after the trace event is enabled to trap all guest mode
      changes.
      
      The MC bit causes Guest Hardware Field Change (GHFC) exceptions whenever
      a guest mode change occurs (such as an exception entry or return from
      exception), so we need to handle this exception now. The MC bit is only
      enabled when restoring register state, so enabling the trace event won't
      take immediate effect.
      
      Tracing guest mode changes can be particularly handy when trying to work
      out what a guest OS gets up to before something goes wrong, especially
      if the problem occurs as a result of some previous guest userland
      exception which would otherwise be invisible in the trace.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: "Radim Krčmář" <rkrcmar@redhat.com>
      Cc: Steven Rostedt <rostedt@goodmis.org>
      Cc: Ingo Molnar <mingo@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      edec9d7b
    • James Hogan's avatar
      KVM: MIPS/VZ: Support hardware guest timer · f4474d50
      James Hogan authored
      Transfer timer state to the VZ guest context (CP0_GTOffset & guest
      CP0_Count) when entering guest mode, enabling direct guest access to it,
      and transfer back to soft timer when saving guest register state.
      
      This usually allows guest code to directly read CP0_Count (via MFC0 and
      RDHWR) and read/write CP0_Compare, without trapping to the hypervisor
      for it to emulate the guest timer. Writing to CP0_Count or CP0_Cause.DC
      is much less common and still triggers a hypervisor GPSI exception, in
      which case the timer state is transferred back to an hrtimer before
      emulating the write.
      
      We are careful to prevent small amounts of drift from building up due to
      undeterministic time intervals between reading of the ktime and reading
      of CP0_Count. Some drift is expected however, since the system
      clocksource may use a different timer to the local CP0_Count timer used
      by VZ. This is permitted to prevent guest CP0_Count from appearing to go
      backwards.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: "Radim Krčmář" <rkrcmar@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      f4474d50
    • James Hogan's avatar
      KVM: MIPS/VZ: Emulate MAARs when necessary · d42a008f
      James Hogan authored
      Add emulation of Memory Accessibility Attribute Registers (MAARs) when
      necessary. We can't actually do anything with whatever the guest
      provides, but it may not be possible to clear Guest.Config5.MRP so we
      have to emulate at least a pair of MAARs.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: "Radim Krčmář" <rkrcmar@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Jonathan Corbet <corbet@lwn.net>
      Cc: Steven Rostedt <rostedt@goodmis.org>
      Cc: Ingo Molnar <mingo@redhat.com>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      Cc: linux-doc@vger.kernel.org
      d42a008f
    • James Hogan's avatar
      KVM: MIPS/VZ: Support guest load-linked bit · 273819a6
      James Hogan authored
      When restoring guest state after another VCPU has run, be sure to clear
      CP0_LLAddr.LLB in order to break any interrupted atomic critical
      section. Without this SMP guest atomics don't work when LLB is present
      as one guest can complete the atomic section started by another guest.
      
      MIPS VZ guest read of CP0_LLAddr causes Guest Privileged Sensitive
      Instruction (GPSI) exception due to the address being root physical.
      Handle this by reporting only the LLB bit, which contains the bit for
      whether a ll/sc atomic is in progress without any reason for failure.
      
      Similarly on P5600 a guest write to CP0_LLAddr also causes a GPSI
      exception. Handle this also by clearing the guest LLB bit from root
      mode.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: "Radim Krčmář" <rkrcmar@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      273819a6