Merge tag 'juno-fixes-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into next/dt64

Pull "ARMv8 Juno DT fixes for v4.12" from Sudeep Holla:

1. Couple of fixes to remove device tree warnings introduced with
   recently added checks in DTC

2. Add information about L1 and L2 caches to Juno device trees as
   CCSIDR-based cacheinfo probing is now removed

* tag 'juno-fixes-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
  arm64: dts: juno: add information about L1 and L2 caches
  arm64: dts: juno: fix few unit address format warnings
  arm64: dts: juno: fix PCI bus dtc warnings

mvebu dt64 for 4.12 (part 2)

- crypto engine description for the Armada 7k/8k SoCs and the boards
  using it
- SDHCI description for the Armada 37xx and 7k/8k SoCs and the boards
  using it

* tag 'mvebu-dt64-4.12-2' of git://git.infradead.org/linux-mvebu:
  arm64: marvell: dts: enable the crypto engine on the Armada 8040 DB
  arm64: marvell: dts: enable the crypto engine on the Armada 7040 DB
  arm64: marvell: dts: add crypto engine description for 7k/8k
  arm64: dts: marvell: add sdhci support for Armada 7K/8K
  arm64: dts: marvell: add eMMC support for Armada 37xx
Signed-off-by: Olof Johansson <olof@lixom.net>

ARM64: DT: Hisilicon SoC DT updates for 4.12

- Reset the hi6220 mmc hosts to avoid hang
- Add the binding for the hi3798cv200 SoC and the poplar board
- Add basic dts files to support the hi3798cv200 poplar board
- Enable the Mbigen, XGE, RoCE and SAS for the hip07 d05 board
- Add driver strength MACRO for the hi3660 SoC
- Add the pinctrl dtsi file for hikey960 board to configure the pins

* tag 'hisi-arm64-dt-for-4.12' of git://github.com/hisilicon/linux-hisi:
  arm64: dts: hisi: add pinctrl dtsi file for HiKey960 development board
  arm64: dts: hisi: add drive strength levels of the pins for Hi3660 SoC
  arm64: dts: hisi: enable the NIC and SAS for the hip07-d05 board
  arm64: dts: hisi: add SAS nodes for the hip07 SoC
  arm64: dts: hisi: add RoCE nodes for the hip07 SoC
  arm64: dts: hisi: add network related nodes for the hip07 SoC
  arm64: dts: hisi: add mbigen nodes for the hip07 SoC
  arm64: dts: hisilicon: add dts files for hi3798cv200-poplar board
  dt-bindings: arm: hisilicon: add bindings for hi3798cv200 SoC and Poplar board
  arm64: dts: hi6220: Reset the mmc hosts
Signed-off-by: Olof Johansson <olof@lixom.net>

Merge tag 'zte-dt64-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt64

ZTE arm64 device tree updates for 4.12:
 - Add mmc devices for ZX296718 SoC and enable those available on
   zx296718-evb board.
 - Add VOU controller device, output devices HDMI and TVENC, and enable
   display support for zx296718-evb board.
 - Remove pll_vga clock from ZX296718 device tree, as it's not a fixed
   rate clock.

* tag 'zte-dt64-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  arm64: dts: zte: add tvenc device for zx296718
  arm64: dts: zte: add vou and hdmi devices for zx296718
  arm64: dts: zte: add mmc devices for zx296718
  arm64: dts: zte: remove zx296718 pll_vga clock
Signed-off-by: Olof Johansson <olof@lixom.net>

Merge tag 'imx-dt64-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt64

Freescale arm64 device tree updates for 4.12:
 - Add support of LS2088A SoC, which is a derivative of existing
   LS2080A SoC, and the major difference is on ARM cores.
 - Add support of LS1088A SoC which includes eight Cortex-A53 cores
   with 32 KB L1 D-cache and I-cache respectively.
 - Add crypto and thermal device support for LS1012A platform.
 - Add ECC register region for SATA device on LS1012A, LS1043A and
   LS1046A platforms.

* tag 'imx-dt64-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  dt-bindings: arm: Add entry for FSL LS1088A RDB, QDS boards
  dt-bindings: clockgen: Add compatible string for LS1088A
  arm64: dts: Add support for FSL's LS1088A SoC
  arm64: dts: ls1012a: add crypto node
  arm64: dts: ls1012a: add thermal monitor node
  arm64: dts: updated sata node on ls1012a platform
  arm64: dts: added ecc register address to sata node on ls1046a
  arm64: dts: added ecc register address to sata node on ls1043a
  arm64: dts: freescale: ls2088a: Add DTS support for FSL's LS2088A SoC
  arm64: dts: freescale: ls2080a: Split devicetree for code resuability
  dt-bindings: Add compatible for LS2088A QDS and RDB board
Signed-off-by: Olof Johansson <olof@lixom.net>

Merge tag 'v4.12-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt64

Basic support for new rk3328, a 4-core Cortex-A53 soc and a fix for the
default memory definition on the px5 eval board. While the bootloader
should already override it with the actual amount, it's better to not
carry around wrong values.

* tag 'v4.12-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  arm64: dts: rockchip: fix the memory size of PX5 Evaluation board
  arm64: dts: rockchip: add RK3328 eavluation board devicetree
  dt-bindings: document rockchip rk3328-evb board
  arm64: dts: rockchip: add core dtsi file for RK3328 SoCs
  dt-bindings: add binding for rk3328-grf
Signed-off-by: Olof Johansson <olof@lixom.net>

Merge tag 'samsung-dt64-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt64

Samsung DeviceTree ARM64 update for v4.12:
1. Add IR, touchscreen and panel to TM2/TM2E boards.
2. Add proper clock frequency properties to DSI nodes.

* tag 'samsung-dt64-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  arm64: dts: exynos: Add the burst and esc clock frequency properties to DSI node
  arm64: dts: exynos: Add support for S6E3HA2 panel device on TM2 board
  arm64: dts: exynos: Add stmfts touchscreen node for TM2 and TM2E
  arm64: dts: exynos: Enable ir-spi in the TM2 and TM2E boards
Signed-off-by: Olof Johansson <olof@lixom.net>

Merge tag 'renesas-arm64-dt2-for-v4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt64

Second Round of Renesas ARM64 Based SoC DT Updates for v4.12

Corrections:
* r8a7795: Correct SATA device size to 2MiB for r8a7795 SoC

Cleanup:
* Drop _clk suffix from X12 clock node name for r8a7795 SoC

Enhancements:
* Add reset control properties for r8a779[56]

* tag 'renesas-arm64-dt2-for-v4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  arm64: dts: r8a7795: salvator-x: Drop _clk suffix from X12 clock node name
  arm64: dts: r8a7796: Add reset control properties
  arm64: dts: r8a7795: Add reset control properties
  arm64: dts: r8a7795: Correct SATA device size to 2MiB
Signed-off-by: Olof Johansson <olof@lixom.net>

Merge tag 'qcom-arm64-for-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/dt64

Qualcomm ARM64 Updates for v4.12

* Fixup MSM8996 SMP2P and add ADSP PIL / SLPI SMP2P node
* Replace PMU compatible w/ A53 specific one
* Add APQ8016 ramoops
* Update MSM8916 hexagon node
* Add PM8994 RTC

* tag 'qcom-arm64-for-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux:
  arm64: dts: msm8996: Add ADSP PIL node
  arm64: dts: qcom: pm8994: Add rtc node
  arm64: dts: apq8016-sbc: Add ramoops
  arm64: dts: qcom: msm8916: Update hexagon node
  arm64: dts: msm8996: Add SLPI SMP2P dt node.
  arm64: dts: qcom: Replace PMU compatible with a53 specific one
  arm64: dts: qcom: msm8996: Fixup smp2p node
Signed-off-by: Olof Johansson <olof@lixom.net>

Merge tag 'tegra-for-4.12-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt64

arm64: tegra: Device tree changes for v4.12-rc1

This adds a bunch of features for Tegra186, such as PMC, ethernet, I2C,
SDHCI and GPIO. It also enables various features on the P2771 devkit.

A small fix is made to the compatible string list for the flow
controller on Tegra132 and the IOMMU is enabled for host1x on Tegra210.

* tag 'tegra-for-4.12-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  arm64: tegra: Update the Tegra132 flowctrl compatible string
  arm64: tegra: Add GPU node for Tegra186
  arm64: tegra: Enable IOMMU for host1x on Tegra210
  arm64: tegra: Enable VIC on Tegra210
  arm64: tegra: Add GPIO expanders on P2771
  arm64: tegra: Add power monitors on P2771
  arm64: tegra: Add GPIO keys on P2771
  arm64: tegra: Enable current monitors on P3310
  arm64: tegra: Enable SD/MMC slot on P2771
  arm64: tegra: Enable SDHCI controllers on P3110
  arm64: tegra: Add initial power tree for P3310
  arm64: tegra: Enable ethernet on P3310
  arm64: tegra: Enable I2C controllers on P3310
  arm64: tegra: Invert the PMC interrupt on P3310
  arm64: tegra: Add ethernet support for Tegra186
  arm64: tegra: Add PMC controller on Tegra186
Signed-off-by: Olof Johansson <olof@lixom.net>

Merge tag 'sunxi-dt-h5-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/dt64

Allwinner H5 DT changes for 4.12

H5 patches for 4.12, which are mostly related to reworking the H3 DTSI to
be usable on the arm64 H5 DTSI, that shares almost everything with the H3
but the CPU cores.

We then have patches to support the H5 boards on top.

* tag 'sunxi-dt-h5-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  ARM: sunxi: h3/h5: switch apb0-related clocks to r_ccu
  arm64: allwinner: h5: enable USB OTG on Orange Pi PC 2 board
  arm64: allwinner: h5: add support for the Orange Pi PC 2 board
  arm64: allwinner: h5: add Allwinner H5 .dtsi
  ARM: sunxi: h3/h5: add usb_otg and OHCI/EHCI for usbc0 on H3/H5
  arm: sun8i: h3: split Allwinner H3 .dtsi
  arm: sun8i: h3: correct the GIC compatible in H3 to gic-400
  arm: sun8i: h3: drop pinctrl-a10.h inclusion for H3 DTSI
  arm: sun8i: h3: drop skeleton.dtsi inclusion in H3 DTSI
Signed-off-by: Olof Johansson <olof@lixom.net>

Merge tag 'sunxi-dt64-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/dt64

Allwinner arm64 DT changes for 4.12

Some patches to enable the PRCM block in the A64

* tag 'sunxi-dt64-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  arm64: allwinner: a64: add R_PIO pinctrl node
  arm64: allwinner: a64: add r_ccu node
Signed-off-by: Olof Johansson <olof@lixom.net>

Merge tag 'amlogic-dt64-redo' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/dt64

Amlogic 64-bit DT updates for v4.12
- pinctrl: new pins for audio
- clocks: more clocks exposed for GFX, audio
- new board: Khadas Vim (S905X)
- new board: HwaCom AmazeTV (S905X)
- ethernet phy: add GPIO resets

* tag 'amlogic-dt64-redo' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: (41 commits)
  ARM64: dts: meson-gx: Add support for HDMI output
  ARM64: dts: meson-gx: Add shared CMA dma memory pool
  ARM64: dts: meson-gxbb-odroidc2: Enable SARADC node
  dt-bindings: clock: gxbb-clkc: Add GXL compatible variant
  clk: meson-gxbb: Expose GP0 dt-bindings clock id
  clk: meson-gxbb: Add MALI clock IDS
  dt-bindings: clk: gxbb: expose i2s output clock gates
  ARM64: dts: meson-gxl: add spdif output pins
  ARM64: dts: meson-gxl: add i2s output pins
  ARM64: dts: meson-gxbb: add spdif output pins
  ARM64: dts: meson-gxbb: add i2s output pins
  ARM64: dts: meson-gxbb: Add USB Hub GPIO hog
  ARM: dts: meson8b: Add gpio-ranges properties
  ARM: dts: meson8: Add gpio-ranges properties
  ARM64: dts: meson-gxl: Add gpio-ranges properties
  ARM64: dts: meson-gxbb: Add gpio-ranges properties
  ARM64: dts: meson-gx: Add Mali nodes for GXBB and GXL
  ARM64: dts: meson-gxl: Add missing pinctrl pins groups
  ARM64: dts: meson-gx: Prepend GX generic compatible like other nodes
  ARM64: dts: meson-gx: empty line cleanup
  ...
Signed-off-by: Olof Johansson <olof@lixom.net>

Commit a8d4636f ("arm64: cacheinfo: Remove CCSIDR-based cache
information probing") removed mechanism to extract cache information
based on CCSIDR register as the architecture explicitly states no
inference about the actual sizes of caches based on CCSIDR registers.

Commit 9a802431 ("arm64: cacheinfo: add support to override cache
levels via device tree") had already provided options to override cache
information from the device tree.

This patch adds the information about L1 and L2 caches on all variants
of Juno platform.

Cc: Will Deacon <will.deacon@arm.com>
Cc: Liviu Dudau <liviu.dudau@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>

This patch fixes the following set of warnings on juno.

 smb@08000000 unit name should not have leading 0s
 sysctl@020000 simple-bus unit address format error, expected "20000"
 apbregs@010000 simple-bus unit address format error, expected "10000"
 mmci@050000 simple-bus unit address format error, expected "50000"
 kmi@060000 simple-bus unit address format error, expected "60000"
 kmi@070000 simple-bus unit address format error, expected "70000"
 wdt@0f0000 simple-bus unit address format error, expected "f0000"
Acked-by: Liviu Dudau <liviu.dudau@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>

Enable the cryptographic engine available in the CP110 master on the
Armada 8040 DB. Do not enable the one in the CP110 salve for now, as we
do not support multiple cryptographic engines yet.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

Enable the cryptographic engine available in the CP110 master on the
Armada 7040 DB.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

Add the description of the crypto engine hardware block for the Marvell
Armada 7k and Armada 8k processors; for both the CP110 slave and master.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

Also enable it on the Armada 7040 DB and Armada 8040 DB boards.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

Add the eMMC support for Armada 37xx SoC and enable it in the Armada 3720
DB board.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

Add pinctrl dtsi file for HiKey960 development board, enable
5 pinmux devices and 1 pinconf device, also include some nodes
of configurations for pins.
Signed-off-by: Wang Xiaoyin <hw.wangxiaoyin@hisilicon.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>

Extend drive strength levels of the pins for Hi3660 Soc.
Signed-off-by: Wang Xiaoyin <hw.wangxiaoyin@hisilicon.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>

Enable the NIC and SAS nodes for the hip07-d05 board
to support related functions.
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>

Add 3 SAS host controller nodes and the dependent subctrl node
to enable the SAS and SATA function for the hip07 SoC.
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>

Add the infiniband node to support the RoCE function
on the hip07 SoC.
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>

Add MDIO, SerDes, Port and realted HNS nodes to support the
network on the hip07 SoC.
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>

Add mbigen nodes for the hip07 SoC those will be used
for the SAS, XGE and PCIe host controllers.
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>

Commit 122682b2abb6 ("arm64: dts: rockchip: Add PX5 Evaluation board")
sets the memory size to 2 GB, but this board only has 1 GB DRAM, so change
it to the correct value here.

Fixes: 122682b2abb6 ("arm64: dts: rockchip: Add PX5 Evaluation board")
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

Add basic dts files for hi3798cv200-poplar board. Poplar is the
first development board compliant with the 96Boards Enterprise
Edition TV Platform specification. The board features the
Hi3798CV200 with an integrated quad-core 64-bit ARM Cortex A53
processor and high performance Mali T720 GPU.
Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
Reviewed-by: Alex Elder <elder@linaro.org>
Acked-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>

Add bindings for HiSilicon hi3798cv200 SoC and Poplar Board.
Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
Reviewed-by: Alex Elder <elder@linaro.org>
Acked-by: Peter Griffin <peter.griffin@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>

The MMC hosts could be left in an unconsistent or uninitialized state from
the firmware. Instead of assuming, the firmware did the right things, let's
reset the host controllers.

This change fixes a bug when the mmc2/sdio is initialized leading to a hung
task:

[  242.704294] INFO: task kworker/7:1:675 blocked for more than 120 seconds.
[  242.711129]       Not tainted 4.9.0-rc8-00017-gcf0251f #3
[  242.716571] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message.
[  242.724435] kworker/7:1     D    0   675      2 0x00000000
[  242.729973] Workqueue: events_freezable mmc_rescan
[  242.734796] Call trace:
[  242.737269] [<ffff00000808611c>] __switch_to+0xa8/0xb4
[  242.742437] [<ffff000008d07c04>] __schedule+0x1c0/0x67c
[  242.747689] [<ffff000008d08254>] schedule+0x40/0xa0
[  242.752594] [<ffff000008d0b284>] schedule_timeout+0x1c4/0x35c
[  242.758366] [<ffff000008d08e38>] wait_for_common+0xd0/0x15c
[  242.763964] [<ffff000008d09008>] wait_for_completion+0x28/0x34
[  242.769825] [<ffff000008a1a9f4>] mmc_wait_for_req_done+0x40/0x124
[  242.775949] [<ffff000008a1ab98>] mmc_wait_for_req+0xc0/0xf8
[  242.781549] [<ffff000008a1ac3c>] mmc_wait_for_cmd+0x6c/0x84
[  242.787149] [<ffff000008a26610>] mmc_io_rw_direct_host+0x9c/0x114
[  242.793270] [<ffff000008a26aa0>] sdio_reset+0x34/0x7c
[  242.798347] [<ffff000008a1d46c>] mmc_rescan+0x2fc/0x360

[ ... ]

Cc: stable@vger.kernel.org
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>

The current practice is to not add _clk suffixes to clock node names in
DT, as these names are used as the actual clock names.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

Amlogic clock headers and DT binding updates for v4.12
- add clocks for I2S and Mali

# gpg: Signature made Tue Apr  4 16:07:50 2017 PDT using RSA key ID D3FBC665
# gpg: Good signature from "Kevin Hilman <khilman@kernel.org>" [ultimate]
# gpg:                 aka "Kevin Hilman <khilman@deeprootsystems.com>" [ultimate]
# gpg:                 aka "Kevin Hilman <khilman@gmail.com>" [ultimate]
# gpg:                 aka "Kevin Hilman <khilman@baylibre.com>" [ultimate]

* tag 'amlogic-clk-headers':
  dt-bindings: clock: gxbb-clkc: Add GXL compatible variant
  clk: meson-gxbb: Expose GP0 dt-bindings clock id
  clk: meson-gxbb: Add MALI clock IDS
  dt-bindings: clk: gxbb: expose i2s output clock gates

Add HDMI output and connector nodes.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>

The HDMI modes needs more CMA memory to be reserved at boot-time.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>

Now that 3adbf342 "iio: adc: add a driver for the SAR ADC found in
Amlogic Meson SoCs" has added support for the ADC, let's enable it
on Odroid C2.
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/1490178747-14837-6-git-send-email-narmstrong@baylibre.com

This patch exposes the GP0 PLL clock id in the dt bindings.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/1490178747-14837-5-git-send-email-narmstrong@baylibre.com

Add missing MALI clock IDs and expose the muxes and gates in the dt-bindings.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/1490177935-9646-2-git-send-email-narmstrong@baylibre.com

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20170309104154.28295-10-jbrunet@baylibre.com