- 13 Sep, 2019 40 commits
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Jing Zhou authored
[Why] DP1.2 LL CTS test failure. [How] The failure is caused by not verify stream link is equal to link, only check stream and link is not null. Signed-off-by:
Jing Zhou <Jing.Zhou@amd.com> Reviewed-by:
Wenjing Liu <Wenjing.Liu@amd.com> Acked-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Charlene Liu authored
[Description] 1. OUTSTANDING_REQUEST_LIMIT update from 0xFF to 0x1F (HW doc update) 2. using memory type to convert UMC's MCLK to Yclk. Signed-off-by:
Charlene Liu <charlene.liu@amd.com> Reviewed-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
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Bayan Zabihiyan authored
[Why] Edid Utility wishes to include DSC module from driver instead of doing it's own logic which will need to be updated every time someone modifies the driver logic. [How] Modify some functions such that we dont need to pass the entire DC structure as parameter. -Remove DC inclusion from module. -Filter out problematic types and inclusions Signed-off-by:
Bayan Zabihiyan <bayan.zabihiyan@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Jaehyun Chung authored
[Why] Underflow occurs on some display setups(repro'd on 3x4K HDR) on boot, mode set, and hot-plugs with. Underflow occurs because mem clk is not set high after disabling pstate switching. This behaviour occurs because some calculations assumed displays were synchronized. [How] Add a condition to check if timing sync is disabled so that synchronized vblank can be set to false. Signed-off-by:
Jaehyun Chung <jaehyun.chung@amd.com> Reviewed-by:
Alvin Lee <Alvin.Lee2@amd.com> Acked-by:
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Jun Lei authored
[why] dc_destroy should only clean up SW, this is because GPUs may be removed before driver unload, leading to HW to be unavailable. [how] remove GPIO close as part of GPIO destroy, this is unnecessary because GPIO is not shared, and GPIOs are generally closed after being opened Add tracking to HW access during destructor to make future issues easier to pinpoint, and block access to prevent hangs. Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Acked-by:
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Vitaly Prosyak authored
[Why & How] Use dcn2 blender, shaper, 3dlut registers Signed-off-by:
Vitaly Prosyak <vitaly.prosyak@amd.com> Reviewed-by:
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Dmytro Laktyushkin authored
Remove code used to allow compilation error free interface change. Signed-off-by:
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Dmytro Laktyushkin authored
New behaviour will track global updates and update any hw that isn't related to current stream being updated. This should fix any issues caused by pipe split pipes being taken by other streams. Signed-off-by:
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Ilya Bakoulin authored
[Why] - Need to add missing surface address register definitions. - RGBE+A does not work in a stereo configuration because surface addresses are no programmed correctly. [How] Added the register definitions and surface address programming. Signed-off-by:
Ilya Bakoulin <Ilya.Bakoulin@amd.com> Reviewed-by:
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Anthony Koo authored
Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Reviewed-by:
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Nikola Cornij authored
[why] It's sometimes useful to have this option when debugging [how] Add a config flag. If the flag is not set, use driver default policy. If the flag is set, use the value from the flag as the starting DSC slice height. Signed-off-by:
Nikola Cornij <nikola.cornij@amd.com> Reviewed-by:
Martin Leung <Martin.Leung@amd.com> Acked-by:
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Nikola Cornij authored
[why] The requirement has been clarified and only DSC 4:2:2 Native has to be disabled. Signed-off-by:
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Alvin Lee authored
We should not allocate payloads if the link is lost until the link is retrained. Some displays require this. Signed-off-by:
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Krunoslav Kovac authored
[Why&How] Driver defaults to 1-tap subsample mode for 4:2:2. DCE11.2 added 3-tap. The policy is: DCE8-DCE11 - change to 2-tap, it's better than 1-tap. DCE11.2+ - use 3-tap Note that 4:2:0 was added in DCE11.2 and already uses 3-tap always. Note 2 is that DCE not covered on Linux, only DCN+ Signed-off-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Reviewed-by:
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Lewis Huang authored
[Why] When user mode use i2c over aux through ADL or DDI, the function dal_ddc_service_query_ddc_data will be called. There are two issues. 1. When read/write length > 16byte, current always return false because the DEFAULT_AUX_MAX_DATA_SIZE != length. 2. When usermode only need to read data through i2c, driver will write mot = true at the same address and cause i2c sink confused. Therefore the following read command will get garbage. [How] 1. Add function dal_dcc_submit_aux_command to handle length > 16 byte. 2. Check read size and write size when query ddc data. Signed-off-by:
Lewis Huang <Lewis.Huang@amd.com> Reviewed-by:
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Ilya Bakoulin authored
[Why] DML diags tests are failing because the struct contents get clobbered by a memcpy. [How] Remove the memcpy call. Signed-off-by:
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Yong Zhao authored
The issue was accidentally introduced recently. Signed-off-by:
Yong Zhao <Yong.Zhao@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Tao Zhou authored
ras recovery_init should be called after ttm init, bad page reserve should be put in front of gpu reset since i2c may be unstable during gpu reset. add cleanup for recovery_init and recovery_fini v2: add more comment and print. remove cancel_work_sync in recovery_init. Signed-off-by:Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
Guchun Chen <guchun.chen@amd.com> Signed-off-by:
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Tao Zhou authored
save umc error records to ras bad page array v2: add bad pages before gpu reset v3: add NULL check for adev->umc.funcs Signed-off-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by:
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Tao Zhou authored
support eeprom records load and save for ras, move EEPROM records storing to bad page reserving v2: remove redundant check for con->eh_data Signed-off-by:
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Tao Zhou authored
change bps type from retired page to eeprom table record, prepare for saving umc error records to eeprom Signed-off-by:
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Andrey Grodzovsky authored
Fix typo which messed up the calculation. Signed-off-by:
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Andrey Grodzovsky authored
Restoring clock gating break SMU opeartion afterwards, avoid this until this further invistigated with SMU. Signed-off-by:
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Andrey Grodzovsky authored
Protect from concurrent SMU accesses. Signed-off-by:
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Roman Li authored
[Why] The earlier patch "Hook up calls to do stereo mux and dig programming..." doesn't include update for dcn21. [How] Align dcn21 gpio settings with updated stereo control interface. Signed-off-by:
Roman Li <Roman.Li@amd.com> Acked-by:
Aaron Liu <aaron.liu@amd.com> Signed-off-by:
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Yong Zhao authored
This optimizes out the pci device id usage in KFD and makes the code more maintainable. Signed-off-by:
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Felix Kuehling authored
These wptrs must be pinned and GPU accessible when this is called from hqd_load functions. So they should never fault. This resolves a circular lock dependency issue involving four locks including the DQM lock and mmap_sem. Signed-off-by:
Oak Zeng <Oak.Zeng@amd.com> Signed-off-by:
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Aaron Liu authored
With stutter mode enabled, NMI prints frequently. Disable stutter for the moment because NMI warning storm, and will enable it back till the issue is addressed Signed-off-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Aaron Liu authored
This patch updates MP1_BASE in renoir_ip_offset.h Signed-off-by:
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Prike Liang authored
With the common interface print_clk_levels can get the following dpm clock: -pp_dpm_dcefclk -pp_dpm_fclk -pp_dpm_mclk -pp_dpm_sclk -pp_dpm_socclk Signed-off-by:
Prike Liang <Prike.Liang@amd.com> Reviewed-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
Kevin Wang <kevin1.wang@amd.com> Signed-off-by:
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John Clements authored
Removed redundant goto statement Signed-off-by:
John Clements <john.clements@amd.com> Reviewed-by:
Feifei Xu <Feifei.Xu@amd.com> Signed-off-by:
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John Clements authored
Add support for loading XGMI/RAS FW Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Tao Zhou authored
change r type from bool to int, suitable for both bool and int return value Signed-off-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Kevin Wang authored
fix bellow patch issue: drm/amd/powerplay: introduce smu table id type to handle the smu table for each asic ---- "This patch introduces new smu table type, it's to handle the different smu table defines for each asic with the same smu ip." before: use smu->table_count to represent the actual table count in smc firmware use actual table count to check smu function parameter about smu table after: use logic table count "SMU_TABLE_COUNT" to check function parameter because table id already mapped in smu driver, and smu function will use logic table id not actual table id to check func parameter. v2: squash in warning fix Signed-off-by:
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Jack Zhang authored
add sw_fini interface of df_funcs. This interface will remove sysfs file of df_cntr_avail function. The old behavior only create sysfs of df_cntr_avail in sw_init, but never remove it for lack of sw_fini interface. With this,driver will report create sysfs fail when it's loaded for the second time. Signed-off-by:
Jack Zhang <Jack.Zhang1@amd.com> Reviewed-by:
Jonathan Kim <Jonathan.Kim@amd.com> Signed-off-by:
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Hawking Zhang authored
UMC RAS feature requires access to UMC & RSMU registers Signed-off-by:
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Hawking Zhang authored
amdgpu_nbio_ras_late_init is used to init nbio specfic ras debugfs/sysfs node and nbio specific interrupt handler. It can be shared among nbio generations Signed-off-by:
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Hawking Zhang authored
amdgpu_mmhub_ras_late_init is used to init mmhub specfic ras debugfs/sysfs node and mmhub specific interrupt handler. It can be shared among mmhub generations Signed-off-by:
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Hawking Zhang authored
amdgpu_sdma_ras_late_init is used to init sdma specfic ras debugfs/sysfs node and sdma specific interrupt handler. It can be shared among sdma generations Signed-off-by:
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Hawking Zhang authored
amdgpu_gfx_ras_late_init is used to init gfx specfic ras debugfs/sysfs node and gfx specific interrupt handler. It can be shared among gfx generations Signed-off-by:
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