- 06 Dec, 2017 40 commits
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Harry Wentland authored
Signed-off-by:
Harry Wentland <harry.wentland@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
Alex Deucher <alexander.deucher@amd.com>
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Harry Wentland authored
arr_points[1] and [2] were duplicated. Remove the extra one. If we ever need more points we can add them but the current state of affairs is confusing. Signed-off-by:
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Tony Cheng authored
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Eric Yang authored
Temporary solution to fix gamma adjustment not working. Signed-off-by:
Eric Yang <Eric.Yang2@amd.com> Reviewed-by:
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Yongqiang Sun authored
New scaler parameter assign to dpp is after early return, cause next flip scaler not program. Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
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Tony Cheng authored
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Eric Bernstein authored
Signed-off-by:
Eric Bernstein <eric.bernstein@amd.com> Reviewed-by:
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Ken Chalmers authored
The ALLOW_SR registers might not always be available. Signed-off-by:
Ken Chalmers <ken.chalmers@amd.com> Reviewed-by:
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SivapiriyanKumarasamy authored
Signed-off-by:
SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com> Reviewed-by:
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Hersen Wu authored
SMU can future lower voltages in long idle case when all display is off. If all display output is turned off via DPMS, send display_count = 0 after all output are turned off. otherwise send display_count msg before turning on display to make sure SMU exit S0i2 state. before is not neccessary as we are out of S0i2 when driver execute code, but send message before anyways for correctness. Signed-off-by:
Hersen Wu <hersenxs.wu@amd.com> Reviewed-by:
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Yongqiang Sun authored
Optimized front end initial sequence, reset MPC module properly. Signed-off-by:
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Dmytro Laktyushkin authored
Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
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Dmytro Laktyushkin authored
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Dmytro Laktyushkin authored
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Dmytro Laktyushkin authored
When new coefficients match cached we would skip setting regamma mode Also, when doing a stream update we would program regamma for all pipes, even thos that are not yet powered on. This resulted in never setting regamma since we would cache before the pipe is powered. Signed-off-by:
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Harry Wentland authored
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Harry Wentland authored
Trying to align with kernel coding style and make it a bit more readable. Signed-off-by:
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Yongqiang Sun authored
There are different code to disable front end, it is difficult to debug and adding new process. This refactor makes all disable front end call the same functions. Signed-off-by:
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Tony Cheng authored
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Yue Hin Lau authored
Signed-off-by:
Yue Hin Lau <Yuehin.Lau@amd.com> Reviewed-by:
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Tony Cheng authored
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Yue Hin Lau authored
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Eric Bernstein authored
Added a function to blank data using OPP DPG. Clean up code to prepare for pseudocode review with HW. Signed-off-by:
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Tony Cheng authored
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Dmytro Laktyushkin authored
This saves us about 5000 reg writes per full update. This translates to about 40000 writes over the course of single eDP bootup. Signed-off-by:
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Andrew Jiang authored
dc_link is at a higher level than link_encoder, and we only want higher-level components to be able to access lower-level ones, not the other way around. Signed-off-by:
Andrew Jiang <Andrew.Jiang@amd.com> Reviewed-by:
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Harry Wentland authored
Previous code threw a warning about misleading indentation Signed-off-by:
Mikita Lipski <Mikita.Lipski@amd.com> Acked-by:
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Yongqiang Sun authored
Clear OPTC underflow status when init_hw. Signed-off-by:
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Yongqiang Sun authored
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Eric Yang authored
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Yue Hin Lau authored
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Eric Bernstein authored
Also move some register definitions to common DCN regs. Signed-off-by:
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Tony Cheng authored
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Yue Hin Lau authored
no logic change Signed-off-by:
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Charlene Liu authored
Signed-off-by:
Charlene Liu <charlene.liu@amd.com> Reviewed-by:
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Yue Hin Lau authored
following the naming convention with correct prefix Signed-off-by:
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Yue Hin Lau authored
dcn version of update_dchub now uses hubbub instead of hwseq Signed-off-by:
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Colin Ian King authored
Variable pf2vf_ver is assigned but never read, it is redundant and hence can be removed. Cleans up clang warning: drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c:310:3: warning: Value stored to 'pf2vf_ver' is never read Reivewed-by:
Horace Chen <horace.chen@amd.com> Signed-off-by:
Colin Ian King <colin.king@canonical.com> Signed-off-by:
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Piotr Redlewski authored
When UVD bo is created, its size is based on the information from firmware header (ucode_size_bytes). The same value should be be used when programming UVD mc controller offsets, otherwise it can happen that (mmUVD_VCPU_CACHE_OFFSET2 + mmUVD_VCPU_CACHE_SIZE2) will point AMDGPU_GPU_PAGE_SIZE bytes after the UVD bo end. Second issue is that when programming the mmUVD_VCPU_CACHE_SIZE0 register, AMDGPU_UVD_FIRMWARE_OFFSET should be taken into account. If it isn't, (mmUVD_VCPU_CACHE_OFFSET2 + mmUVD_VCPU_CACHE_SIZE2) will always point AMDGPU_UVD_FIRMWARE_OFFSET bytes after the UVD bo end. v2: move firmware size calculation into macro definition v3: align firmware size to the gpu page size Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Piotr Redlewski <predlewski@gmail.com> Signed-off-by:
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Mikita Lipski authored
This feature synchronizes multiple displays with various timings to a display with the highest refresh rate it is enabled if edid caps flag multi_display_sync is set to one There are limitations on refresh rates allowed that can be synchronized. That would prevent from underflow and other potential corruptions. Multi display synchronization is using the same functions as timing_sync in order to minimize redunduncy and decision to disable synchronization is based on trigger parametre set in DM Feature is developed for DCN1 and DCE11 Signed-off-by:
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