DWC3 Exynos Specific Glue layer can be used only for Exynos SoCs.
In addition, non-DT for EXYNOS SoCs is not supported from v3.11;
thus, there is no need to support non-DT for DWC3 Exynos Specific
Glue layer.

The 'linux/platform_data/dwc3-exynos.h' file has been used for
non-DT support. Thus, the 'dwc3-exynos.h' file is removed, because
it is not used anymore.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

Since the DCPCTR doesn't have the ACLRM bit, the usbus_pipe_clear()
should not call the usbhsp_pipectrl_set() with ACLRM.
So, this patch fixes this issue to add the usbhs_fifo_clear_dcp()
in fifo.c because the controller needs the CFIFO to clear the
the DCP PIPE.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

According to the datasheet, this driver should clear the INTSTS0.CTRT
bit before this controller detects the next stage transition. Otherwise,
the driver may not be able to clear the bit after the controller went to
the next stage transition. After that, the driver will not be able to
clear the INTSTS0.VALID, and a usb control transfer will not finish
finally.

If we use the testusb tool, it is easy to reproduce this issue:

 # testusb -a -t 10

Since the previous code handled a data stage and a status stage in
the usbhsf_pio_try_push(), it may not clear the INTSTS0.CTRT at the
right timing.
So, this patch change the timing of usbhs_dcp_control_transfer_done()
to the usbhsg_irq_ctrl_stage().
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

This patch fixes an issue that this driver always enable the D+ pullup
after it detected the VBUS connection even though this usb controller
can control the D+ pullup timing by software. So, this driver should
enable the D+ pullup after a gadget driver called usb_gadget_connect().
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

This patch fixes an issue that the NULL pointer dereference happens
when we uses g_audio driver. Since the g_audio driver will call
usb_ep_disable() in afunc_set_alt() before it calls usb_ep_enable(),
the uep->pipe of renesas usbhs driver will be NULL. So, this patch
adds a condition to avoid the oops.
Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Fixes: 2f98382d (usb: renesas_usbhs: Add Renesas USBHS Gadget)
Cc: <stable@vger.kernel.org> # v3.0+
Signed-off-by: Felipe Balbi <balbi@ti.com>

This patch allows the gadget portion of the DWC2 driver to get built when
(!USB && USB_GADGET) condition is encountered.
Acked-by: Paul Zimmerman <paulz@synopsys.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

HIRD threshold should be configurable by different platforms.

From DesignWare databook:
When HIRD_Threshold[4] is set to 1b1 and HIRD value is greater than or
equal to the value in HIRD_Threshold[3:0], dwc3 asserts output signals
utmi_l1_suspend_n to put PHY into Deep Low-Power mode in L1.

When HIRD_Threshold[4] is set to 1b0 or the HIRD value is less than
HIRD_Threshold[3:0], dwc3 asserts output signals utmi_sleep_n on L1.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

This patch adds support for AMD Nolan (NL) FPGA and SoC platform.

Cc: Jason Chang <jason.chang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

The AMD Nolan (NL) SoC contains a DesignWare USB3 Dual-Role Device that can
be operated either as a USB Host or a USB Device.  In the AMD NL platform,
this device ([1022:7912]) has a class code of PCI_CLASS_SERIAL_USB_XHCI
(0x0c0330), which means the xhci driver will claim it.

But the dwc3 driver is a more specific driver for this device, and we'd
prefer to use it instead of xhci.  To prevent xhci from claiming the
device, change the class code to 0x0c03fe, which the PCI r3.0 spec defines
as "USB device (not host controller)".  The dwc3 driver can then claim it
based on its Vendor and Device ID.
Suggested-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Jason Chang <jason.chang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

This patch adds PCI id for USB3 Dual-Role Device of AMD Nolan (NL) SoC.
It will be used for PCI quirks and DWC3 device driver.
Signed-off-by: Jason Chang <jason.chang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

This patch adds disable usb2 suspend phy quirk, and some special platforms
can configure that if it is needed.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

This patch adds disable usb3 suspend phy quirk, and some special platforms
can configure that if it is needed.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

This patch adds Tx de-emphasis quirk, and the Tx de-emphasis value is
configurable according to PIPE3 specification.

Value		Description
0		-6dB de-emphasis
1		-3.5dB de-emphasis
2		No de-emphasis
3		Reserved

It can be configured on DT or platform data.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

It is recommended to set USB3 and USB2 SUSPHY bits to '1' after the core
initialization is completed above the dwc3 revision 1.94a.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

This patch adds RX_DETECT to Polling.LFPS control quirk, and some special
platforms can configure that if it is needed.

[ balbi@ti.com : added DeviceTree binding documentation ]
Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

This patch adds LFPS filter quirk, and some special platforms can configure
that if it is needed.

[ balbi@ti.com : added DeviceTree binding documentation ]
Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

This patch adds delay PHY power change from P0 to P1/P2/P3 when link state
changing from U0 to U1/U2/U3 respectively, and some special platforms can
configure that if it is needed.

[ balbi@ti.com : added DeviceTree binding documentation ]
Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

This patch adds delay P0 to P1/P2/P3 quirk for U2/U2/U3, and some special
platforms can configure that if it is needed.

[ balbi@ti.com : added DeviceTree binding documentation ]
Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

This patch adds request P1/P2/P3 quirk for U2/U2/U3, and some special
platforms can configure that if it is needed.

[ balbi@ti.com : added DeviceTree binding documentation ]
Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

This patch adds P3 in U2 SS inactive quirk, and some special platforms can
configure that if it is needed.

[ balbi@ti.com : added DeviceTree binding documentation ]
Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

This patch adds u2exit lfps quirk, and some special platforms can configure
that if it is needed.

[ balbi@ti.com : added DeviceTree binding documentation ]
Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

When parameter DWC_USB3_LPM_ERRATA_ENABLE is enabled in Andvanced
Configuration of coreConsultant, it supports of xHCI BESL Errata Dated
10/19/2011 is enabled in host mode. In device mode it adds the capability
to send NYET response threshold based on the BESL value received in the LPM
token, and the threhold is configurable for each soc platform.

This patch adds an entry that soc platform is able to define the lpm
capacity with their own device tree or bus glue layer.

[ balbi@ti.com : added devicetree documentation, spelled threshold
		completely, made sure threshold is only applied to
		proper core revisions. ]
Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

This patch adds disscramble quirk, and it only needs to be enabled at fpga
board on some vendor platforms.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

This patch initializes platform data at pci glue layer, and SoCs x86-based
platform vendor is able to define their flags in platform data at bus glue
layer. Then do some independent behaviors at dwc3 core level.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

Some chip vendor is on pre-silicon phase, which needs to use the simulation
board. It should have the same product and vendor id with the true soc, but
might have some minor different configurations.

Below thread discussion proposes to find a method to distinguish between
simulation board and soc.

http://marc.info/?l=linux-usb&m=141194772206369&w=2

In Andvanced Configuration of coreConsultant, there is the parameter of
DWC_USB_EN_FPGA. This bit has the function we need. And it would response as 7
bit of GHWPARAMS6 register. So it's able to check this functional bit to confirm
if works on FPGA board.
Reported-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

It enables hibernation if the function is set in coreConsultant.
Suggested-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

This patch adds support of the PHY framework for ChipIdea drivers.
Changes are done in both the ChipIdea common code and in the drivers
accessing the PHY. This is done by adding a new PHY member in
ChipIdea's structures and by taking care of it in the code.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

This patch modify the generic code handling PHYs to allow them to be
supplied from the drivers. This adds checks to ensure no PHY was already
there when looking for one in the generic code. This also makes sure we
do not modify its state in the generic HCD functions, it was provided by
the driver.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: Alan Stern <stern@rowland.harvard.edu>
Signed-off-by: Felipe Balbi <balbi@ti.com>

This patch adds support of the PHY framework in OTG and keeps the USB
PHY compatibility. Here the only modification is to add PHY member in
the OTG structure, along with the USB PHY one.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

This patch prepares the introduction of the generic PHY support in the
USB OTG common functions. The USB PHY member of the OTG structure is
renamed to 'usb_phy' and modifications are done in all drivers accessing
it. Renaming this pointer will allow to keep the compatibility for USB
PHY drivers.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

Before using the PHY framework instead of the USB PHY one, we need to
move the OTG state into another place, since it won't be available when
USB PHY isn't used. This patch moves the OTG state into the OTG
structure, and makes all the needed modifications in the drivers
using the OTG state.

[ balbi@ti.com : fix build regressions with phy-tahvo.c, musb_dsps.c,
		phy-isp1301-omap, and chipidea's debug.c ]
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
Acked-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

drivers/usb/gadget/udc/r8a66597-udc.c:1849:1-3: WARNING: PTR_ERR_OR_ZERO can be used

 Use PTR_ERR_OR_ZERO rather than if(IS_ERR(...)) + PTR_ERR

Generated by: scripts/coccinelle/api/ptr_ret.cocci
Signed-off-by: Fengguang Wu <fengguang.wu@intel.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

Added failure check for usb_assign_descriptors call in bind function.
Acked-By: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Pavitrakumar Managutte <pavitra1729@gmail.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

In commit 0ec8fd70 ("USB: musb: fix possible panic while resuming")
musb_resume() became musb_resume_early() in order to enable the clocks
early on resume. This piece of the resume code was removed later in
commit 03491761 ("usb: musb: move clock handling to glue layer").
In between the function was renamed from musb_resume_early() to
musb_resume_noirq() by commit commit 48fea965 ("USB: Rework musb
suspend()/resume_early()").

Now I see that first musb_core is resumed followed by phy and glue
layer and I ask myself is this really what we intend to do? This kind
of revoked the purpose of the first commit (0ec8fd70).
Because of this and because it looks wrong to resume (core) before the
glue layer I push it to the ->resume callback.
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Felipe Balbi <balbi@ti.com>

This patch moves calls to phy enable/disable out of spinlock protected
blocks in device suspend/resume to fix incorrect caller context. Phy
related functions must not be called from atomic context. To protect
device internal state from a race during suspend, a call to
s3c_hsotg_core_disconnect() is added under a spinlock, what prevents any
further activity on the usb bus.
Acked-by: Paul Zimmerman <paulz@synopsys.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

This patch moves udc initialization from pullup() method to
s3c_hsotg_udc_start(), so that method ends with hardware fully
initialized and left in soft-disconnected state. After this change, the
pullup() method simply clears soft-disconnect start() when called with
is_on=1. For completeness, a call to s3c_hsotg_core_disconnect() has
been added when pullup() method is called with is_on=0, what puts the
udc hardware back to soft-disconnected state.
Acked-by: Paul Zimmerman <paulz@synopsys.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

This patch moves phy enable/disable calls from pullup() method to
udc_start/stop functions. This solves the issue related to limited caller
context for PHY functions, because they cannot be called from non-sleeping
context. This is also a preparation for using soft-disconnect feature of
udc controller in pullup() method.
Acked-by: Paul Zimmerman <paulz@synopsys.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

This patch changes s3c_hsotg_core_init function to leave hardware in
soft disconnect mode, so the moment of coupling the hardware to the usb
bus can be later controlled by the separate functions for enabling and
disabling soft disconnect mode. This patch is a preparation to rework
pullup() method.
Acked-by: Paul Zimmerman <paulz@synopsys.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

This patch removes duplicated code and sets last_rst variable in the
function which does the hardware reset.
Acked-by: Paul Zimmerman <paulz@synopsys.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

Sanity check on resource happening with devm_ioremap_resource().
Signed-off-by: Varka Bhadram <varkab@cdac.in>
Signed-off-by: Felipe Balbi <balbi@ti.com>