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  19. 22 Jul, 2015 3 commits
    • Peter Griffin's avatar
      ARM: STi: Remove platform call to trace_hardirqs_off() · 50de4dd4
      Peter Griffin authored 
      Calling trace_hardirqs_off() from the platform specific
secondary startup code as not been necessary since Dec 2010
when Russell King consolidated the call into the common SMP
code.

2c0136db ARM: SMP: consolidate trace_hardirqs_off() into common SMP code
Signed-off-by: default avatarPeter Griffin <peter.griffin@linaro.org>
Signed-off-by: default avatarMaxime Coquelin <maxime.coquelin@st.com>
      50de4dd4
    • Peter Griffin's avatar
      ARM: STi: Add code to release secondary cores from holding pen. · 94a8cfce
      Peter Griffin authored 
      Most upstream devs boot STi platform via JTAG which abuses the
boot process by setting the PC of secondary cores directly. As
a consquence, booting STi platforms via u-boot results in only
the primary core being brought up as the code to manage the
holding pen is not upstream.

This patch adds the necessary code to bring the secondary cores
out of the holding pen. It uses the cpu-release-addr DT property
to get the address of the holding pen from the bootloader.

With this patch booting upstream kernels via u-boot works
correctly:

[    0.045456] CPU: Testing write buffer coherency: ok
[    0.045597] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
[    0.045734] Setting up static identity map for 0x40209000 - 0x40209098
[    0.065047] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
[    0.065081] Brought up 2 CPUs
[    0.065089] SMP: Total of 2 processors activated (5983.43 BogoMIPS).
[    0.065092] CPU: All CPU(s) started in SVC mode.
Signed-off-by: default avatarPeter Griffin <peter.griffin@linaro.org>
Acked-by: default avatarMaxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: default avatarMaxime Coquelin <maxime.coquelin@st.com>
      94a8cfce
    • Thomas Betker's avatar
      ARM: zynq: Set bit 22 in PL310 AuxCtrl register (6395/1) · 6632d4fd
      Thomas Betker authored 
      This patch is based on the
commit 1a8e41cd ("ARM: 6395/1: VExpress: Set bit 22 in the PL310
(cache controller) AuxCtlr register")

Clearing bit 22 in the PL310 Auxiliary Control register (shared
attribute override enable) has the side effect of transforming Normal
Shared Non-cacheable reads into Cacheable no-allocate reads.

Coherent DMA buffers in Linux always have a cacheable alias via the
kernel linear mapping and the processor can speculatively load cache
lines into the PL310 controller. With bit 22 cleared, Non-cacheable
reads would unexpectedly hit such cache lines leading to buffer
corruption.

For Zynq, this fix avoids memory inconsistencies between Gigabit
Ethernet controller (GEM) and CPU when DMA_CMA is disabled.
Suggested-by: default avatarPunnaiah Choudary Kalluri <punnaia@xilinx.com>
Signed-off-by: default avatarThomas Betker <thomas.betker@rohde-schwarz.com>
Signed-off-by: default avatarMichal Simek <michal.simek@xilinx.com>
      6632d4fd
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