- 05 Feb, 2014 1 commit
-
-
Imre Deak authored
Bspec and the code suggests that the interrupt signaled by IIR[7,5] (DISPLAY_PIPE_A/B_VBLANK) is a first level IRQ flag for the second level PIPEA/BSTAT[2] (Start of Vertical Blank) interrupt. Measuring the relative timings of when IIR[7] and PIPEASTAT[1,2] get set and checking the effect of unmasking different pipestat and IIR events shows that this isn't so: First, ISR/IIR[7] gets set independently of PIPEASTAT[18] (Start of Vertical Blank Enable) or any other pipestat enable bit, so it isn't a first level IRQ bit showing the state of PIPEASTAT[2], but is connected directly to the timing generator. Second, setting only PIPEASTAT[18] and leaving all other pipestat events disabled, IIR[6] (DISPLAY_PIPE_A_EVENT) gets set close to the moment when PIPEASTAT[2] gets set, so the former is a first level interrupt flag for the latter. The bspec is rather unclear about this, but I also assume that IIR[6] signals all pipestat A events, except PIPEASTAT[31] (FIFO Under-run Status). Third, IIR[7] is set close to the moment when PIPEASTAT[1] (Framestart Interrupt) gets set, in the mode I used about 12usec after PIPEASTAT[2] and IIR[6] gets set. This means the IIR[7] isn't marking the start of vblank, but rather signals the framestart event. Based on the above, we don't need to unmask IIR[7] when waiting for start of vblank events, but we can rely on IIR[6] being always unmasked, which will signal when PIPEASTAT[2] gets set. Doing this will also get rid of the overhead of getting an interrupt and servicing IIR[7], which is atm raised always some time after IIR[6]/PIPEASTAT[2] is raised. Signed-off-by:
Imre Deak <imre.deak@intel.com> Reviewed-by:
Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch>
-
- 04 Feb, 2014 10 commits
-
-
Antti Koskipaa authored
RFCv2: Reorganize array indexing so that full offsets can be used as is. It makes grepping for registers in i915_reg.h much easier. Also move offset arrays to intel_device_info. v1: Fixed offsets for VLV, proper eDP handling v2: Fixed BCLRPAT, PIPESRC, PIPECONF and DSP* macros. v3: Added EDP pipe comment, removed redundant offset arrays for MSA_MISC and DDI_FUNC_CTL. v4: Rename patch and report object size increase. v5: Change location of commas, add PIPE_EDP into enum pipe v6: Insert PIPE_EDP_OFFSET into pipe offset array v7: Set I915_MAX_PIPES back to 3, change more registers accessors to use the new macros, get rid of _PIPE_INC and add dev_priv as a parameter where required by the new macros. Upcoming hardware will not have the various display pipe register ranges evenly spaced in memory. Change register address calculations into array lookups. Tested on SNB, VLV, IVB, Gen2 and HSW w/eDP. I left the UMS cruft untouched. Size differences: text data bss dec hex filename 596431 4634 56 601121 92c21 i915.ko (new) 593199 4634 56 597889 91f81 i915.ko (old) Signed-off-by:Antti Koskipaa <antti.koskipaa@linux.intel.com> Reviewed-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Tested-by:
-
Chris Wilson authored
Since a purged buffer is one without any associated pages, attempting to use it should generate EFAULT rather than EINVAL, as it is not strictly an invalid parameter. Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
-
Chris Wilson authored
EFAULT will be a possible return code where backing storage is transient, such after it is purged by madvise. As such it is to be expected and so should not trigger a WARN inside i915_gem_fault() but be converted silently to SIGBUS. Signed-off-by:
-
Mika Kuoppala authored
Found with smatch. Signed-off-by:
Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by:
-
Mika Kuoppala authored
Found with smatch Signed-off-by:
-
Deepak S authored
When we enter RC6 and GFX Clocks are off, the voltage remains higher than Vmin. When we try to set the freq to RPn, it might fail since the Gfx clocks are down. So to fix this in Gfx idle, Bring the GFX clock up and set the freq to RPn then move GFx down. v2: remove vlv_update_rps_cur_delay function. Update commit message (Daniel) v3: Fix the timeout during wait for gfx clock (Jesse) v4: addressed comments on set freq and punit wait (Ville) v5: use wait_for while waiting for GFX clk to be up. (Daniel) update cur_delay before requesting min_delay. (Ville) v6: use wait_for while waiting for punit. (Ville) Signed-off-by:Deepak S <deepak.s@intel.com> Reviewed-by:
-
Mika Kuoppala authored
As we seek the guilty batch using request and hangcheck score, this code is not needed anymore. v2: Rebase. Passing dev_priv instead of getting it from last_ring Signed-off-by:
-
Mika Kuoppala authored
With full ppgtt using acthd is not enough to find guilty batch buffer. We get multiple false positives as acthd is per vm. Instead of scanning which vm was running on a ring, to find corressponding context, use a different, simpler, strategy of finding batches that caused gpu hang: If hangcheck has declared ring to be hung, find first non complete request on that ring and claim it was guilty. v2: Rebase Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=73652Suggested-by:
-
Ville Syrjälä authored
Both Bspec and the W/A database state that WaDisablePSDDualDispatchEnable is only needed for IVB GT1. The only real confusion here is that the the W/A database also says to write to the GT2 only register as well, which is strange if the W/A is only for GT1. Signed-off-by:
Rodrigo Vivi <rodrigo.vivi@gmail.com> Signed-off-by:
-
Ville Syrjälä authored
IVB GT2 has two registers for these things, and both must be written. To add a bit more confusion both Bspec and the W/A database state that WaDisablePSDDualDispatchEnable is only needed for IVB GT1, but the W/A database also says to write even the second GT2 only register. So I don't really know what the right thing here is. Note that Bspec disagrees with the w/a database here, but Ville confirmed (by asking Chris) that on gt1 the 2nd reg doesn't exist. Signed-off-by:
-
- 30 Jan, 2014 15 commits
-
-
Chris Wilson authored
We want to use the GTT for reading back objects upon an error so that we have exactly the information that the GPU saw. However, it is verboten to access snoopable pages through the GTT and causes my PineView GPU to throw a page fault instead. This has not been a problem in the past as we only dumped ringbuffers and batchbuffers, both of which must be not snooped. However, the introduction of HWS page dumping leads to a read of a snooped object through the GTT. This was introduced by commit f3ce3821 Author: Chris Wilson <chris@chris-wilson.co.uk> Date: Thu Jan 23 22:40:36 2014 +0000 drm/i915: Include HW status page in error capture Signed-off-by:
-
Chris Wilson authored
Repeating the same information multiple times is just annoying. Signed-off-by:
-
Mika Kuoppala authored
If we have stopped rings then we know that test is running so no need for spam. In addition, only spam when default context gets banned. v2: - make sure default context ban gets shown (Chris) - use helper for checking for default context, everywhere (Chris) v3: - dont be quiet when debug is set (Ben, Daniel) Reference: https://bugs.freedesktop.org/show_bug.cgi?id=73652Signed-off-by:Ben Widawsky <ben@bwidawsk.net> Signed-off-by:
-
Mika Kuoppala authored
With full ppgtt support drm_i915_file_private gained knowledge about the default context. Also reset stats are now inside i915_hw_context so we can use proper abstraction. v2: Move BUG_ON and WARN_ON to more proper locations (Ben) v3: Pass dev directly to i915_context_is_banned to avoid the need to dereference ctx->last_ring. Spotted by Mika when checking my s/BUG/WARN/ change, I've missed this ->last_ring dereference. Suggested-by:
-
Chia-I Wu authored
The optimization helps IVB too. No piglit regression. Signed-off-by:
Chia-I Wu <olv@lunarg.com> Reviewed-by:
-
Chia-I Wu authored
The optimization is available on Ivy Bridge and later, and is disabled by default. Enabling it helps certain workloads such as GLBenchmark TRex test. No piglit regression. v2 - no need to save the register before suspend as init_clock_gating can correctly program it after resume - split IVB change to another commit Signed-off-by:
-
Ben Widawsky authored
v2: Rebased upon cleaned up error state v3: Make sure hangcheck info remains last (Chris) Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
-
Ben Widawsky authored
Chris: Do we also want to capture? GAC_ECO_BITS /* gen6,7 */ GAM_ECOCHK /* gen6,7 */ GAB_CTL /* gen6 */ GFX_MODE /* gen6 */ Requested-by:
-
Ben Widawsky authored
v2: Moved num_requests up (Chris) Rebased on new hws page capture which required a rename since it made two members named, 'hws' in the per ring error state. (Ben) Signed-off-by:
-
Ben Widawsky authored
This helps make an upcoming patch a bit more reviewable Signed-off-by:
-
Ben Widawsky authored
Create logical sections in an attempt to clean up, and continue to keep future additions clean. v2: Reworded the comments. Added section headers (Chris) Signed-off-by:
-
Ben Widawsky authored
The code has become quite hairy. By relocating all the generic registers it will become more obvious where future ones should go. There is still admittedly a bit of confusion left for things like per ring registers. A subsequent patch will clean this function up. Signed-off-by:
-
Daniel Vetter authored
Backmerge drm-next - I need to backmerge drm-intel-fixes patches touching the error capture code to be able to merge Ben's cleanup patches. Conflicts: drivers/gpu/drm/i915/i915_gpu_error.c Signed-off-by: -
Dave Airlie authored
Merge branch 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6 into drm-next more fixes for nouveau. * 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6: drm/nouveau: resume display if any later suspend bits fail drm/nouveau: fix lock unbalance in nouveau_crtc_page_flip drm/nouveau: implement hooks for needed for drm vblank timestamping support drm/nouveau/disp: add a method to fetch info needed by drm vblank timestamping drm/nv50: fill in crtc mode struct members from crtc_mode_fixup
-
git://people.freedesktop.org/~agd5f/linuxDave Airlie authored
more radeon fixes * 'drm-next-3.14' of git://people.freedesktop.org/~agd5f/linux: drm/radeon/dce8: workaround for atom BlankCrtc table drm/radeon/DCE4+: clear bios scratch dpms bit (v2) drm/radeon: set si_notify_smc_display_change properly drm/radeon: fix DAC interrupt handling on DCE5+ drm/radeon: clean up active vram sizing drm/radeon: skip async dma init on r6xx drm/radeon/runpm: don't runtime suspend non-PX cards drm/radeon: add ring to fence trace functions drm/radeon: add missing trace point drm/radeon: fix VMID use tracking
-
- 29 Jan, 2014 14 commits
-
-
Ilia Mirkin authored
If either idling channels or suspending the fence were to fail, the display would never be resumed. Also if a client fails, resume the fence (not functionally important, but it would potentially leak memory). See https://bugs.freedesktop.org/show_bug.cgi?id=70213Signed-off-by:
Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
-
Maarten Lankhorst authored
Fixes a regression introduced by d5c1e84b "drm/nouveau: hold mutex while syncing to kernel channel". Cc: stable@vger.kernel.org #3.13 Reported-by:
Fengguang Wu <fengguang.wu@intel.com> Signed-off-by:
Maarten Lankhorst <maarten.lankhorst@canonical.com> Signed-off-by:
-
Ben Skeggs authored
Signed-off-by: -
Ben Skeggs authored
Signed-off-by: -
Ben Skeggs authored
The DRM uses the adjusted mode to calculate constants for vblank timestamping. Our encoder mode_fixup (usually) replaces this data with our backend mode information, which doesn't have the needed data filled in already. Reported-by: Mario Kleiner mario.kleiner.de@gmail.com Signed-off-by: -
Daniel Vetter authored
Request by Ben Widawsky in his review of a patch touching this code. v2: Clarify the disdinction between evicting vmas (to free up virtual address space) and evicting objects (to free up actual system memory). Suggested by Ben. Cc: Ben Widawsky <benjamin.widawsky@intel.com> Acked-by:
Ben Widawsky <benjamin.widawsky@intel.com> Signed-off-by:
-
Alex Deucher authored
Some DCE8 boards have a funky BlankCrtc table that results in a timeout when trying to blank the display. The timeout is harmless (all operations needed from the table are complete), but wastes time and is confusing to users so work around it. bug: https://bugs.freedesktop.org/show_bug.cgi?id=73420Signed-off-by:
Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
-
Alex Deucher authored
The BlankCrtc table in some DCE8 boards has some logic shortcuts for the vbios when this bit is set. Clear it for driver use. v2: fix typo Bug: https://bugs.freedesktop.org/show_bug.cgi?id=73420Signed-off-by:
-
Alex Deucher authored
This is effectively a revert of 4573388c. Forcing a display active when there is none causes problems with dpm on some SI boards which results in improperly initialized dpm state and boot failures on some boards. As for the bug commit 4573388c tried to address, one can manually force the state to high for better performance when using the card as a headless compute node until a better fix is developed. bugs: https://bugs.freedesktop.org/show_bug.cgi?id=73788 https://bugs.freedesktop.org/show_bug.cgi?id=69395Signed-off-by:
-
Chris Wilson authored
During eviction, we are only considering how to free up space within the current address space and not concerned with freeing up physical memory. As such we need only skip nodes that pinned in the current VM and not globally. Signed-off-by:
-
Alex Deucher authored
DCE5 and newer hardware only has 1 DAC. Use the correct offset. This may fix display problems on certain board configurations. Signed-off-by: -
Alex Deucher authored
If we are not able to properly initialize one of the gpu engines for buffer paging, we limit vram to the size of the cpu visible aperture. We generally either use the gfx or dma engine to do this. Clean up the size limiting code to only adjust the size based on what ring is selected for buffer paging rather than making assumptions about which engine is selected for paging. Signed-off-by:
Christian König <christian.koenig@amd.com>
-
Alex Deucher authored
The hw is buggy and it's not currently used, but it's currently still initialized by the driver. Skip the init. Skipping init also seems to improve stability with dpm on some r6xx asics. bug: https://bugs.freedesktop.org/show_bug.cgi?id=66963Signed-off-by:
-
Alex Deucher authored
Prevent runtime suspend of non-PX GPUs. Runtime suspend is not what we want in those cases. Signed-off-by:
-
