- 24 Aug, 2020 7 commits
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Furquan Shaikh authored
drivers: gpu: amd: Initialize amdgpu_dm_backlight_caps object to 0 in amdgpu_dm_update_backlight_caps In `amdgpu_dm_update_backlight_caps()`, there is a local `amdgpu_dm_backlight_caps` object that is filled in by `amdgpu_acpi_get_backlight_caps()`. However, this object is uninitialized before the call and hence the subsequent check for aux_support can fail since it is not initialized by `amdgpu_acpi_get_backlight_caps()` as well. This change initializes this local `amdgpu_dm_backlight_caps` object to 0. Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Furquan Shaikh <furquan@google.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Dewar authored
In init_powerplay_table_information() the value returned from kmalloc() is cast unnecessarily. Remove cast. Issue identified with Coccinelle. Signed-off-by:
Alex Dewar <alex.dewar90@gmail.com> Signed-off-by:
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Wang Hai authored
Remove asic_reg/nbio/nbio_6_1_offset.h which is included more than once Reviewed-by:
Evan Quan <evan.quan@amd.com> Reported-by:
Hulk Robot <hulkci@huawei.com> Signed-off-by:
Wang Hai <wanghai38@huawei.com> Signed-off-by:
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Lukas Bulwahn authored
Besides the intended change, commit 4cc1178e ("drm/amdgpu: replace DRM prefix with PCI device info for gfx/mmhub") also set the source files mmhub_v1_0.c and gfx_v9_4.c to be executable, i.e., changed fromold mode 644 to new mode 755. Commit 241b2ec9 ("drm/amd/display: Add dcn30 Headers (v2)") added the four header files {dpcs,dcn}_3_0_0_{offset,sh_mask}.h as executable, i.e., mode 755. Set to the usual modes for source and headers files and clean up those mistakes. No functional change. Reviewed-by:
Lukas Bulwahn <lukas.bulwahn@gmail.com> Signed-off-by:
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Dennis Li authored
if other threads have holden the reset lock, recovery will fail to try_lock. Therefore we introduce atomic hive->in_reset and adev->in_gpu_reset, to avoid reentering GPU recovery. v2: drop "? true : false" in the definition of amdgpu_in_reset Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
Dennis Li <Dennis.Li@amd.com> Signed-off-by:
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Nicholas Kazlauskas authored
[Why] These aren't stable on some platform configurations when driving multiple displays, especially on higher resolution. In particular the delay in asserting p-state and validating from x86 outweights any power or performance benefit from the hardware composition. Under some configurations this will manifest itself as extreme stutter or unresponsiveness especially when combined with cursor movement. [How] Disable these for now. Exposing overlays to userspace doesn't guarantee that they'll be able to use them in any and all configurations and it's part of the DRM contract to have userspace gracefully handle validation failures when they occur. Valdiation occurs as part of DC and this in particular affects RV, so disable this in dcn10_global_validation. Signed-off-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by:
Hersen Wu <hersenxs.wu@amd.com> Signed-off-by:
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Mukul Joshi authored
Add __user annotation to fix related sparse warning while reading SDMA counters from userland. Also, rework the read SDMA counters function by removing redundant checks. Reported-by:
kernel test robot <lkp@intel.com> Signed-off-by:
Mukul Joshi <mukul.joshi@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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- 18 Aug, 2020 20 commits
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Alexander Monakov authored
Documentation for sysfs backlight level interface requires that values in both 'brightness' and 'actual_brightness' files are interpreted to be in range from 0 to the value given in the 'max_brightness' file. With amdgpu, max_brightness gives 255, and values written by the user into 'brightness' are internally rescaled to a wider range. However, reading from 'actual_brightness' gives the raw register value without inverse rescaling. This causes issues for various userspace tools such as PowerTop and systemd that expect the value to be in the correct range. Introduce a helper to retrieve internal backlight range. Use it to reimplement 'convert_brightness' as 'convert_brightness_from_user' and introduce 'convert_brightness_to_user'. Bug: https://bugzilla.kernel.org/show_bug.cgi?id=203905 Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1242 Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by:
Alexander Monakov <amonakov@ispras.ru> Signed-off-by:
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Tong Zhang authored
core_link_read_dpcd returns only DC_OK(1) and DC_ERROR_UNEXPECTED(-1), the caller should check error using DC_OK instead of checking against 0 Signed-off-by:
Tong Zhang <ztong0001@gmail.com> Signed-off-by:
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Colin Ian King authored
The 32 bit unsigned integer bl_pwm is being shifted using 32 bit arithmetic and then being assigned to a 64 bit unsigned integer. There is a potential for a 32 bit overflow so cast bl_pwm to enforce a 64 bit shift operation to avoid this. Addresses-Coverity: ("unintentional integer overflow") Fixes: 3ba01817 ("drm/amd/display: Move panel_cntl specific register from abm to panel_cntl.") Signed-off-by:Colin Ian King <colin.king@canonical.com> Signed-off-by:
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Alex Deucher authored
We can get this on RENOIR and newer via the SMU metrics table. Reviewed-by:
Nirmoy Das <nirmoy.das@amd.com> Signed-off-by:
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Alex Deucher authored
Grab the data from the SMU metrics table. Reviewed-by:
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Alex Deucher authored
Grab the data from the SMU metrics table. Reviewed-by:
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Alex Deucher authored
FAMILY_KV is APUs and we already check for APUs. Reviewed-by:
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Leo Liu authored
Fix warning from kernel test robot v2: remove the local variable as well Signed-off-by:
Leo Liu <leo.liu@amd.com> Reviewed-by:
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jqdeng authored
Use function printk_ratelimit to limit the print rate. Signed-off-by:
jqdeng <Emily.Deng@amd.com> Acked-by:
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jqdeng authored
Only for no job running test case need to do recover in flr notification. For having job in mirror list, then let guest driver to hit job timeout, and then do recover. Signed-off-by:
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Evan Quan authored
Considering the same logic can be applied to Arcturus, Navi1X and Sienna Cichlid. Signed-off-by:
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Evan Quan authored
Add deep sleep disablement/enablement on UMD pstate entering/exiting. Signed-off-by:
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Evan Quan authored
Considering the same logic can be applied to Arcturus, Navi1X and Sienna Cichlid. Signed-off-by:
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Evan Quan authored
Add gfx ulv disablement/enablement on UMD pstate entering/exiting. Signed-off-by:
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Jiansong Chen authored
It's in accordance with pmfw 65.7.0 for navy_flounder. Signed-off-by:
Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
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Jiansong Chen authored
This reverts commit ba4e049e. Newly released sdma fw (51.52) provides a fix for the issue. Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
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Luben Tuikov authored
Remove DRM_SCHED_PRIORITY_INVALID. We no longer carry around an invalid priority and cut it off at the source. Backwards compatibility behaviour of AMDGPU CTX IOCTL passing in garbage for context priority from user space and then mapping that to DRM_SCHED_PRIORITY_NORMAL is preserved. v2: Revert "res" --> "r" and "prio" --> "priority". Signed-off-by:Luben Tuikov <luben.tuikov@amd.com> Reviewed-by:
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Luben Tuikov authored
Remove DRM_SCHED_PRIORITY_LOW, as it was used in only one place. Rename and separate by a line DRM_SCHED_PRIORITY_MAX to DRM_SCHED_PRIORITY_COUNT as it represents a (total) count of said priorities and it is used as such in loops throughout the code. (0-based indexing is the the count number.) Remove redundant word HIGH in priority names, and rename *KERNEL* to *HIGH*, as it really means that, high. v2: Add back KERNEL and remove SW and HW, in lieu of a single HIGH between NORMAL and KERNEL. Signed-off-by: -
Bhawanpreet Lakha authored
Without this, enabling dsc will cause a nullptr Reviewed-by:
Mikita Lipski <Mikita.Lipski@amd.com> Signed-off-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Acked-by:
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Mukul Joshi authored
To prevent reporting erroneous SDMA usage, initialize SDMA activity counter to 0 before using. Signed-off-by:
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- 17 Aug, 2020 13 commits
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Bhawanpreet Lakha authored
This field is not defined for DCN3 Signed-off-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
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Anthony Koo authored
[Header Changes] - Add command for panel power seq control Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Jaehyun Chung authored
[Why] DSC will be disabled if DPCD 0006F[6:3] is set to a non-zero value because bits 6:3 are not currently supported. When 6:3 is populated, an unsupported INCREMENT OF bits_per_pixel value is read (DPCD 0006F[2:0]) [How] Mask the INCREMENT OF bits_per_pixel field so that values in the unsupported field are ignored. Signed-off-by:
Jaehyun Chung <jaehyun.chung@amd.com> Reviewed-by:
Wenjing Liu <Wenjing.Liu@amd.com> Acked-by:
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Krunoslav Kovac authored
[Why&How] pow(a,x) is implemented as exp(x*log(a)). log(0) will crash. So return 0^x = 0, unless x=0, convention seems to be 0^0 = 1. Cc: stable@vger.kernel.org Signed-off-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Reviewed-by:
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Chris Park authored
[Why] Programming is missing the sequence where for eDP the scrambling is reset when testing for eye diagram test pattern. [How] Include the required register in the definition Signed-off-by:
Chris Park <Chris.Park@amd.com> Reviewed-by:
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Lewis Huang authored
[Why] For some special panel, it will have an invalid HPD high cause driver DPCD read/write fail. [How] Add extra T3 delay as a monitor patch in dce110_edp_wait_for_hpd_ready Signed-off-by:
Lewis Huang <Lewis.Huang@amd.com> Reviewed-by:
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Eryk Brol authored
[why] Previously when force enabling DSC on SST display we unknowingly supressed lane count, which caused DSC to be enabled automatically. [how] By adding an additional flag to force enable DSC in dc_dsc.c DSC can always be enabled with debugfs dsc_clock_en forced to 1 Cc: stable@vger.kernel.org Signed-off-by:
Eryk Brol <eryk.brol@amd.com> Signed-off-by:
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Dmytro Laktyushkin authored
Wide timing DSC requires odm. Since spreadsheet is missing this dsc validation we have to modify DML vba code ourselves. Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
Wesley Chalmers <Wesley.Chalmers@amd.com> Acked-by:
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Qingqing Zhuo authored
[why] Current pipe merge and split logic only supports cases where new dc_state is allocated and relies on dc->current_state to gather information from previous dc_state. Calls to validate_bandwidth on UPDATE_TYPE_MED would cause an issue because there is no new dc_state allocated, and data in dc->current_state would be overwritten during pipe merge. [how] Only allow validate_bandwidth when new dc_state space is created. Signed-off-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Reviewed-by:
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Yongqiang Sun authored
[Why & How] Add read backlight interface to get ABM data. Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
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hersen wu authored
[Why] with eDP + DP, each display use one pipe. after DP unplugged, eDP switch from one pipe to two pipes -- pipe split. dpp1_cm_set_regamma_pwl will be executed too. The duration from switch single pipe to dual pipes is a little long which could let eDP enter PSR mode. upon two pipes for eDP are setup, eDP PHY is disabled. front pipe is not really running to fetch data from frame buffer. i.e., dchubp is not in normal working status. execution of hubbub1_wm_change_req_wa may cause p-state warning. [How] disable eDP PSR before dc_commit_state. psr is disabled when execute hubbub1_wm_change_req_wa. Signed-off-by:
Roman Li <Roman.Li@amd.com> Acked-by:
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Paul Hsieh authored
[Why] Place the cursor in the center of screen between two pipes then adjusting the viewport but cursour doesn't update cause DFPstate hang. [How] If viewport changed, update cursor as well. Cc: stable@vger.kernel.org Signed-off-by:
Paul Hsieh <paul.hsieh@amd.com> Reviewed-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
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Yongqiang Sun authored
[Why & How] change abm config init interface to support multiple ABMs. Signed-off-by:
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