- 20 Dec, 2011 2 commits
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Stephen Warren authored
tegra20_pinmux_init() is called from the pinmux's probe() function, and hence should be __devinit not __init. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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Olof Johansson authored
Update the defconfig for tegra due to the addition of tegra30 and rename of t20/t30 options. Signed-off-by: Olof Johansson <olof@lixom.net> Acked-by: Stephen Warren <swarren@nvidia.com>
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- 18 Dec, 2011 16 commits
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Peter De Schrijver authored
Add support for the tegra30 based cardhu development board. Cardhu is a tablet formfactor reference design for tegra30. The patch provides a device tree for the board, updates Makefile.boot to build the dtb, includes the platform in Kconfig and updates board-dt.c. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Colin Cross <ccross@android.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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Peter De Schrijver authored
Add support for tegra30 SoC. This includes a device tree compatible type for this SoC ("nvidia,tegra30") and adds L2 cache initialization for this new SoC. The clock framework is still missing, which prevents most drivers from working. The basic IRQs are the same, so remove the dependency on CONFIG_ARCH_TEGRA_2x_SOC. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Colin Cross <ccross@android.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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Peter De Schrijver authored
Define the pinmuxing and pindrive tables for tegra30. The pinmux table defines the available functions for each pinmux group. The pindrive table defines the default pullup or pulldowns for each group. Derived from code by Scott Williams (scwilliams@nvidia.com) Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Colin Cross <ccross@android.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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Peter De Schrijver authored
Add new fields to struct tegra_pingroup_desc to support new hardware features introduced in the tegra30 SoC. The pinmux driver won't use those fields yet, but the tegra30 pinmux tables will already provide the necessary data. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Colin Cross <ccross@android.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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Peter De Schrijver authored
This patch modifies the pinmux code to be useable for multiple tegra variants. Some tegra20 specific constants will be replaced by variables which will be initialized to the appropriate value at runtime. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Colin Cross <ccross@android.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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Peter De Schrijver authored
Rename pinmux-t2.h and pinmux-t2-tables.c to the new tegra naming. This file will be reworked somewhat in the next patch to support multiple tegra SoC types. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Colin Cross <ccross@android.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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Peter De Schrijver authored
Generalize L2 cache initialization and discover L2 cache associativity at runtime. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Colin Cross <ccross@android.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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Peter De Schrijver authored
Use PMC reset rather then CAR system reset as recommended by the hardware team. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Colin Cross <ccross@android.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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Peter De Schrijver authored
Tegra20 based boards will be handled by the current board-dt.c file. Tegra30 based boards will be handled by a new board-dt-tegra30.c file. Hence rename the existing board-dt.c to board-dt-tegra20.c to reflect its use. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Colin Cross <ccross@android.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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Peter De Schrijver authored
This patch splits the early init code in a common and a tegra20 specific part. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Colin Cross <ccross@android.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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Peter De Schrijver authored
don't export clk_measure_input_freq as its functionality is also available using clk_get_rate(). Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Colin Cross <ccross@android.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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Peter De Schrijver authored
Rework the tegra20 clock code to support multiple tegra variants : * remove tegra2_periph_reset_assert/tegra2_periph_reset_deassert. This functionality should be in clock.c. * remove tegra_sdmmc_tap_delay and export tegra2_sdmmc_tap_delay directly. This feature is handled inside the sdmmc block from tegra30 onwards. So there is no need for support in the clock code beyond tegra20. There are no in tree users of this function. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Colin Cross <ccross@android.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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Peter De Schrijver authored
* add a dependency to ARCH_TEGRA_2x_SOC in Kconfig to all tegra20 based boards and TEGRA_PCI * make powergating dependent on ARCH_TEGRA_2x_SOC * remove dependency on ARCH_TEGRA_2x_SOC for clock.c Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Colin Cross <ccross@android.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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Peter De Schrijver authored
The timer and rtc-timer clocks aren't gated by default, so there is no reason to crash the system if the dummy enable call failed. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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Olof Johansson authored
Conflicts: arch/arm/mach-tegra/board-dt.c Signed-off-by: Olof Johansson <olof@lixom.net>
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Peter De Schrijver authored
This patch adds the initial device tree for tegra30 Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Colin Cross <ccross@android.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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- 12 Dec, 2011 4 commits
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Will Deacon authored
Now that there is a common way to reset the machine, let's use it instead of reinventing the wheel in the kexec backend. Signed-off-by: Will Deacon <will.deacon@arm.com>
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Will Deacon authored
Sending IPI_CPU_STOP to a CPU causes it to execute a busy cpu_relax loop forever. This makes it impossible to kexec successfully on an SMP system since the secondary CPUs do not reset. This patch adds a callback to platform_cpu_kill, defined when CONFIG_HOTPLUG_CPU=y, from the ipi_cpu_stop handling code. This function currently just returns 1 on all platforms that define it but allows them to do something more sophisticated in the future. Signed-off-by: Will Deacon <will.deacon@arm.com>
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Will Deacon authored
Tools such as kexec and CPU hotplug require a way to reset the processor and branch to some code in physical space. This requires various bits of jiggery pokery with the caches and MMU which, when it goes wrong, tends to lock up the system. This patch fleshes out the soft_restart implementation so that it branches to the reset code using the identity mapping. This requires us to change to a temporary stack, held within the kernel image as a static array, to avoid conflicting with the new view of memory. Signed-off-by: Will Deacon <will.deacon@arm.com>
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Will Deacon authored
When disabling the MMU, it is necessary to take out a 1:1 identity map of the reset code so that it can safely be executed with and without the MMU active. To avoid the situation where the physical address of the reset code aliases with the virtual address of the active stack (which cannot be included in the 1:1 mapping), it is desirable to change to a new stack at a location which is less likely to alias. This code adds a new lib function, call_with_stack: void call_with_stack(void (*fn)(void *), void *arg, void *sp); which changes the stack to point at the sp parameter, before invoking fn(arg) with the new stack selected. Reviewed-by: Nicolas Pitre <nicolas.pitre@linaro.org> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Dave Martin <dave.martin@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
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- 11 Dec, 2011 1 commit
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Jamie Iles authored
When probing the VIC, the ST variant has a different probing method to account for the extra interrupts which meant we didn't previously call vic_register() which registered the irq_domain. Acked-by: Linus Walleij <linus.walleij@stericsson.com> Cc: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Jamie Iles <jamie@jamieiles.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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- 08 Dec, 2011 17 commits
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Russell King authored
Merge branch 'for-rmk' of git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas/linux into devel-stable Conflicts: arch/arm/mm/ioremap.c
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Catalin Marinas authored
This patch adds the ARM_LPAE and ARCH_PHYS_ADDR_T_64BIT Kconfig entries allowing LPAE support to be compiled into the kernel. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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Will Deacon authored
Memory banks living outside of the 32-bit physical address space do not have a 1:1 pa <-> va mapping and therefore the __va macro may wrap. This patch ensures that such banks are marked as highmem so that the Kernel doesn't try to split them up when it sees that the wrapped virtual address overlaps the vmalloc space. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Nicolas Pitre <nico@linaro.org>
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Catalin Marinas authored
With LPAE, the pgd is a separate page table with entries pointing to the pmd. The identity_mapping_add() function needs to ensure that the pgd is populated before populating the pmd level. The do..while blocks now loop over the pmd in order to have the same implementation for the two page table formats. The pmd_addr_end() definition has been removed and the generic one used instead. The pmd clean-up is done in the pgd_free() function. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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Catalin Marinas authored
With LPAE, TTBRx registers are 64-bit. The ASID is stored in TTBR0 rather than a separate Context ID register. This patch makes the necessary changes to handle context switching on LPAE. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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Catalin Marinas authored
The DFSR and IFSR register format is different when LPAE is enabled. In addition, DFSR and IFSR have similar definitions for the fault type. This modifies the fault code to correctly handle the new format. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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Catalin Marinas authored
Similar to the PTE freeing, this patch introduced __pmd_free_tlb() which invalidates the TLB before freeing a PMD page. This is needed because on newer processors the entry in the upper page table may be cached by the TLB and point to random data after the PMD has been freed. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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Catalin Marinas authored
This patch adds the MMU initialisation for the LPAE page table format. The swapper_pg_dir size with LPAE is 5 rather than 4 pages. A new proc-v7-3level.S file contains the TTB initialisation, context switch and PTE setting code with the LPAE. The TTBRx split is based on the PAGE_OFFSET with TTBR1 used for the kernel mappings. The 36-bit mappings (supersections) and a few other memory types in mmu.c are conditionally compiled. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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Catalin Marinas authored
This patch modifies the pgd/pmd/pte manipulation functions to support the 3-level page table format. Since there is no need for an 'ext' argument to cpu_set_pte_ext(), this patch conditionally defines a different prototype for this function when CONFIG_ARM_LPAE. The patch also introduces the L_PGD_SWAPPER flag to mark pgd entries pointing to pmd tables pre-allocated in the swapper_pg_dir and avoid trying to free them at run-time. This flag is 0 with the classic page table format. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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Catalin Marinas authored
This patch introduces the pgtable-3level*.h files with definitions specific to the LPAE page table format (3 levels of page tables). Each table is 4KB and has 512 64-bit entries. An entry can point to a 40-bit physical address. The young, write and exec software bits share the corresponding hardware bits (negated). Other software bits use spare bits in the PTE. The patch also changes some variable types from unsigned long or int to pteval_t or pgprot_t. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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Will Deacon authored
Before we enable the MMU, we must ensure that the TTBR registers contain sane values. After the MMU has been enabled, we jump to the *virtual* address of the following function, so we also need to ensure that the SCTLR write has taken effect. This patch adds ISB instructions around the SCTLR write to ensure the visibility of the above. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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Catalin Marinas authored
This patch modifies the proc-v7.S file so that it only contains code shared between classic MMU and LPAE. The non-common code is factored out into a separate file. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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Catalin Marinas authored
The FSR structure is different with LPAE and this patch moves the classic MMU specific definition to a separate fsr-2level.c file that is included in fault.c. It also moves the fsr_fs and FSR bits to the fault.h file. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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Catalin Marinas authored
The page table maintenance macros need to be duplicated between the classic and the LPAE MMU so this patch moves those that are not common to the pgtable-2level.h file. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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Russell King authored
Nick Piggin noted upon introducing 4level-fixup.h: | Add a temporary "fallback" header so architectures can run with | the 4level pagetables patch without modification. All architectures | should be converted to use the folding headers (include/asm-generic/ | pgtable-nop?d.h) as soon as possible, and the fallback header removed. This makes ARM compliant with this statement. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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Catalin Marinas authored
With the arch/arm code conversion to pgtable-nopud.h, the section and supersection (un|re)map code triggers compiler warnings on UP systems. This is caused by pmd_offset() being given a pgd_t argument rather than a pud_t one. This patch makes the necessary conversion with the assumption that the pud is folded into the pgd. The page table setting code only loops over the pmd which is enough with the classic page tables. This code is not compiled when LPAE is enabled. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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pdeschrijver@nvidia.com authored
Convert tegra20 IRQ intialization to the GIC devicetree binding. Modify the interrupt definitions in the dts files according to Documentation/devicetree/bindings/arm/gic.txt v3 (swarren): * Moved of_irq_init() call into board-dt.c to avoid ifdef'ing it. - Even with a dummy replacement if !CONFIG_OF, the reference from tegra_dt_irq_match[] to gic_of_init() would still have to be ifdef'd - It's plausible that tegra_dt_irq_match[] may need to contain more entries in the future, and defining what they are seems more suitable for board-dt.c than irq.c v2 (swarren): * Removed some stale GIC init code from board-dt.c * Undid some accidental 0x -> 0x0 search/replace. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> [olof: added include of <asm/hardware/gic.h> for compile to pass] Signed-off-by: Olof Johansson <olof@lixom.net>
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