- 09 Jan, 2014 1 commit
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Mike Turquette authored
Merge tag 'for_3.14/samsung-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tfiga/samsung-clk into clk-next-samsung (A bit late) first round of Samsung clock patches for v3.14.
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- 08 Jan, 2014 24 commits
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Tomasz Figa authored
This patch adds a label and #clock-cells property to device node of max77686 PMIC to allow using it as a clock provider. Signed-off-by:
Tomasz Figa <t.figa@samsung.com> Acked-by:
Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by:
Mike Turquette <mturquette@linaro.org>
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Tomasz Figa authored
If max77686 chip is instantiated from device tree, it is desirable to have an OF clock provider to allow device tree based look-up of clocks. This patch adds OF clock provider registration to the clk-max77686 driver. Signed-off-by:
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Tomasz Figa authored
As a prerequisite for further patch adding OF clock provider support to the driver, this patch changes the driver to store an array of struct clk * as driver data. Signed-off-by:
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Tomasz Figa authored
This patch fixes invalid kfree() and adds missing call to clk_unregister() in error and remove paths in max77686_clk_probe(). While at it, error handling is also cleaned up. Signed-off-by:
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Tomasz Figa authored
As a preparation for further patches, this patch modifies the clock registration helper function to return a pointer to the newly registered clock. No functional change is done to the driver. Signed-off-by:
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Tomasz Figa authored
The function can simply return 0, without jumping to a separate label, which does exactly the same. This patch does not introduce any functional change, just a clean-up. Signed-off-by:
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Tomasz Figa authored
It is usually nice to know frequency of a clock, so this patch adds a .recalc_rate() callback returning rates of provided clocks. Signed-off-by:
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Tomasz Figa authored
Changing status of clock gates in max77686 requires i2c transfers, which can sleep, so this is done in prepare and unprepare callbacks. Due to this, checking whether whether the clock is ungated must be done in is_prepared() callback as well, for consistency. Signed-off-by:
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Tomasz Figa authored
This patch adds an entry for Samsung SoC clock drivers located under drivers/clk/samsung/ directory, with me taking the maintainer role. Signed-off-by:
Sachin Kamat <sachin.kamat@linaro.org> Acked-by:
Sylwester Nawrocki <s.nawrocki@samsung.com> Acked-by:
Kukjin Kim <kgene.kim@samsung.com> Acked-by:
Jingoo Han <jg1.han@samsung.com> Signed-off-by:
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Andrew Bresticker authored
Specify the remaining input clocks (pll_ref, pll_in, and sclk_pcm_in) for the AudioSS clock controller. Signed-off-by:
Andrew Bresticker <abrestic@chromium.org> Acked-by:
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Andrew Bresticker authored
The AudioSS block on Exynos 5420 has an additional clock gate for the ADMA bus clock. Signed-off-by:
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Andrew Bresticker authored
Specify pll_ref, pll_in, sclk_audio, and sclk_pcm_in for the AudioSS clock controller. Signed-off-by:
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Andrew Bresticker authored
There is no gate for the PCM clock input to the AudioSS block, so the parent of sclk_pcm is div_pcm0. Add a clock ID for it so that we can reference it in device trees. Signed-off-by:
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Andrew Bresticker authored
This allows the input clocks to the Exynos AudioSS block to be specified via device-tree bindings. Default names will be used when an input clock is not given. Signed-off-by:
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Andrew Bresticker authored
The Exynos AudioSS clock controller will later be modified to allow input clocks to be specified via device-tree in order to support multiple Exynos SoCs. This will introduce a dependency on the core SoC clock controller being initialized first so that the AudioSS driver can look up its input clocks, but the order in which clock providers are probed in of_clk_init() is not guaranteed. Since deferred probing is not supported in of_clk_init() and the AudioSS block is not the core controller, we can initialize it later as a platform device. Signed-off-by:
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Andrzej Hajda authored
The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by:
Andrzej Hajda <a.hajda@samsung.com> Signed-off-by:
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Andrzej Hajda authored
The patch adds header file defining clock IDs. This allows to use macros instead of magic numbers in DT bindings. Signed-off-by:
Andrzej Hajda <a.hajda-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org> Signed-off-by:
Kyungmin Park <kyungmin.park-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org> Acked-by:
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Andrzej Hajda authored
The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by:
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Andrzej Hajda authored
The patch adds header file defining clock IDs. This allows to use macros instead of magic numbers in DT bindings. Signed-off-by:
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Andrzej Hajda authored
The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by:
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Andrzej Hajda authored
The patch adds header file defining clock IDs. This allows to use macros instead of magic numbers in DT bindings. Signed-off-by:
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Andrzej Hajda authored
The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by:
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Andrzej Hajda authored
The patch adds header file defining clock IDs. This allows to use macros instead of magic numbers in DT bindings. Signed-off-by:
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Andrew Bresticker authored
Register the APLL rate table so that we can set the APLL rate from the cpufreq driver. Signed-off-by:
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- 31 Dec, 2013 1 commit
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Mike Turquette authored
Conflicts: drivers/clk/clk.c
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- 30 Dec, 2013 14 commits
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Mike Turquette authored
Merge branch 'for_3.14/keystone-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone into clk-next-keystone
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Sachin Kamat authored
Add CLK_SET_RATE_PARENT flag to mout_apll clock. This will let us set the clock rate in the cpufreq driver. Signed-off-by:
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Tomasz Figa authored
This patch adds mout_aclk333_sub mux clock and updates gate clocks from MFC domain to have it as their parent as specified in SoC documentation. Signed-off-by:
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Tomasz Figa authored
According to SoC documentation, input 5 of mout_audio muxes is connected to xxti (named fin_pll in the driver). This patch corrects defined parent arrays to match SoC documentation. Signed-off-by:
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Tomasz Figa authored
This patch updates mux parent arrays with unpopulated mux inputs, as all inputs need to be specified in parent arrays passed to clk_register_mux(), otherwise clk_set_parent() can generate out of bound accesses to the array. Signed-off-by:
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Tomasz Figa authored
This patch adds mux_aclk_200_disp1_sub mux clock, which according to SoC documentation is the correct parent of DISP1 gate clocks. Signed-off-by:
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Tomasz Figa authored
This patch adds mout_aclk266_gscl_sub mux clock and adjusts definitions of GSCL domain gate clocks to use it as their parent, as specified in SoC documentation. Signed-off-by:
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Tomasz Figa authored
This patch renames all mux clocks to start with mout_ prefix and all div clocks to start with div_ prefix for consistency with other clocks already defined this way. Signed-off-by:
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Tomasz Figa authored
This patch reorders clock definitions, so they are sorted by register addresses and bitfield shifts. When at it, blank lines are added to separate definitions of clocks from different registers. Overall this should make the driver more readable and reduce the number of potential conflicts when adding new entries. Signed-off-by:
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Tomasz Figa authored
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Krzysztof Kozlowski authored
Move reg_save[] into CONFIG_PM_SLEEP dependency block as it is used only by suspend and resume functions. This fixes the warning on CONFIG_PM_SLEEP=n: drivers/clk/samsung/clk-exynos-audss.c:29:22: warning: ‘reg_save’ defined but not used [-Wunused-variable] Signed-off-by:
Krzysztof Kozlowski <k.kozlowski@samsung.com> Acked-by:
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Abhilash Kesavan authored
The sysreg (system register) generates control signals for various blocks like disp1blk, i2c, mipi, usb etc. However, it gets disabled as an unused clock at boot-up. This can lead to failures in operation of above blocks, because they can not be configured properly if this clock is disabled. Signed-off-by:
Abhilash Kesavan <a.kesavan@samsung.com> Acked-by:
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Abhilash Kesavan authored
Due to incorrect clock specified in MDMA0 node, using MDMA0 controller could cause system failures, due to wrong clock being controlled. This patch fixes this by specifying correct clock. Signed-off-by:
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Abhilash Kesavan authored
Adds gate clock for MDMA0 on Exynos5250 SoC. This is needed to ensure that the clock is enabled when MDMA0 is used on systems on which firmware gates the clockby default. Signed-off-by:
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