- 09 Apr, 2012 29 commits
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Daniel Vetter authored
And add informational dmesg output where it does not yet exist. In case a quirk matches too much, this information is crucial for debugging such a bug report. Reviewed-by:
Chris Wilson <chris@chris-wilson.co.uk> Signed-Off-by:
Daniel Vetter <daniel.vetter@ffwll.ch>
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Daniel Vetter authored
It exists way back to gen2, bug got moved around on gen4 a bit. Reviewed-by:
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Chris Wilson authored
Reported-and-tested-by: Bo Wang < bo.b.wang@intel.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=36997Signed-off-by:
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Daniel Vetter authored
Ums is already disabled, but on ilk we can additionally disable gem initialization when using user mode setting. Upstream never support ilk without kernel modesetting and not even the RHEL ilk ums backport needs gem - that driver is based on xf86-video-intel version 2.2, which is pre-gem. Reviewed-by:
Adam Jackson <ajax@redhat.com> Reviewed-by:
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Daniel Vetter authored
Spurred by an irc discussion, let's start to clear up which parts of our kms + ums/gem + ums/dri1 + vbios/dri1 kernel driver pieces userspace in the wild actually uses. The idea is that we introduce checks at entry-points (module load time, ioctls, ...) first and then reap any obviously dead code in a second step. As a first step refuse to load without kms on chips where userspace never supported ums. Now upstream hasn't supported ums on ilk, ever. But RHEL had the great idea to backport the kms support to their ums driver. Cc: Dave Airlie <airlied@gmail.com> Signed-Off-by: -
Daniel Vetter authored
vlv, ivb and snb all share the gen6+ gt irq handling. 3 copies of the same stuff is a bit much, so extract it into a little helper. Now ilk has a different gt irq handling than snb, but shares the same irq handler (due to the similar display block). So also extract the ilk gt irq handling to clearly separate these two things. Nice side effect of this is that we can complete Ben Widawsky's gen6+ irq bit #define cleanup and call the render irq also with the GEN6 alias. Beforehand that code was shared with ilk, and neither option really made much sense. As a bonus this enables the error interrupt handling lifted from the vlv code on snb and ivb, too. Reviewed-by:
Jesse Barnes <jbarnes@virtuousgeek.org> Antagonized-by:
Ben Widawsky <ben@bwidawsk.net> Signed-Off-by:
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Daniel Vetter authored
Top-level interrupt bits are usually found in the display block. It therefore makes sense to use HAS_PCH_SPLIT in i915_irq.c But the irq stuff in intel_ring.c only concerns itself with render core/gt-level interrupt sources. It therefore makes more sense to switch based on gpu gen. Kills a vlv special case. Reviewed-by:
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Daniel Vetter authored
This got copy-pasted from an older version. The newer kinds of workarounds don't need this anymore. Shame on me for not noticing when picking up the vlv irq patch. Reviewed-by:
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Ben Widawsky authored
We can now open-code the get/put irq functions as they were just abstracting single register definitions. It would be nice to merge this in with the IRQ handling code... but that is too much work for me at present. In addition I could probably collapse this in to a lot of the Ironlake stuff, but I don't think it's worth the potential regressions. This patch itself should not effect functionality. CC: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by:
Ben Widawsky <benjamin.widawsky@intel.com> Reviewed-by:
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Ben Widawsky authored
- gen6 put/get only need one argument rflags and gflags are always the same (see above explanation) - remove a couple redundantly defined IRQs - reordered some lines to make things go in descending order Every ring has its own interrupts, enables, masks, and status bits that are fed into the main interrupt enable/mask/status registers. At one point in time it seemed like a good idea to make our functions support the notion that each interrupt may have a different bit position in the corresponding register (blitter parser error may be bit n in IMR, but bit m in blitter IMR). It turned out though that the HW designers did us a solid on Gen6+ and this unfortunate situation has been avoided. This allows our interrupt code to be cleaned up a bit. I jammed this into one commit because there should be no functional change with this commit, and staging it into multiple commits was unnecessarily artificial IMO. CC: Chris Wilson <chris@chris-wilson.co.uk> CC: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: -
Eugeni Dodonov authored
DDIA is detected via the DDI_BUF_CTL registers bit 0, but for DDIB, DDIC and DDID we need to consult SFUSE_STRAP values. Signed-off-by:
Eugeni Dodonov <eugeni.dodonov@intel.com> Reviewed-by:
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Eugeni Dodonov authored
Watermark line time registers for display low power watermark. v2: improve bit names as suggested by Chris Wilson Signed-off-by:
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Eugeni Dodonov authored
The WR PLL can drive the DDI ports at fixed frequencies for HDMI, DVI, DP and FDI. Signed-off-by:
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Eugeni Dodonov authored
Those are used to control the display core clock. v2: change the enable bit setting, spotted by Rodrigo Vivi. Reviewed-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
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Eugeni Dodonov authored
Different registers are identified by their target id and offset. To simplify their programming, they are called as <RegisterName><TargetId>. For example, SSCCTL register accessed through SBI at target id 6 and offset 0c is called SBI_SSCCTL6. Reviewed-by:
Rodrigo Vivi <rodrigo.vivi@gmail.com> Signed-off-by:
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Eugeni Dodonov authored
Multiple clocks can drive different outputs. v2: use the port enums to access individual ports v1 Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> Signed-off-by:
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Eugeni Dodonov authored
This PLL control can drive DDI ports at desired frequencies for DisplayPort and FDI connections. Reviewed-by:
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Eugeni Dodonov authored
Pixel clock gating control for Lynx point. Reviewed-by:
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Eugeni Dodonov authored
Those are responsible for the Sideband Interface programming. v2: rename SBI bits to better reflect their meaning Reviewed-by:
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Eugeni Dodonov authored
Those registers are used to train DDI buffer translations for each link type. v2: access each port registers through the DDI_BUF_TRANS macro Signed-off-by:
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Eugeni Dodonov authored
There is one instance of those registers for each DDI port. v2: access registers via the DDI_BUF_CTL() macro Reviewed-by:
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Eugeni Dodonov authored
There is one set of those registers for each port. Signed-off-by:
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Eugeni Dodonov authored
This is one set of those registers for each pipe. v2: use port enum to access individual registers Signed-off-by:
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Eugeni Dodonov authored
There is one set of such registers for each pipe (A/B/C/EDP). v2: update to use DDI PORTS enum v1 Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
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Eugeni Dodonov authored
There are 5 DDI ports on Haswell. Port A is always enabled, and is the one connected to eDP, and Port E is the one that can be connected to the PCH using FDI protocol. Ports B, C, D and E can be used for digital outputs. Signed-off-by:
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Eugeni Dodonov authored
This defines the registers used by different power wells. Reviewed-by:
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Eugeni Dodonov authored
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Eugeni Dodonov authored
This adds product definitions for desktop, mobile and server boards. v2: split into a separate patch, add .has_pch_split feature. Signed-off-by:
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Eugeni Dodonov authored
The macro is becoming too complex and with VLV upon us it can lead to confusion. So transforming this into a feature check instead. Signed-off-by:
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- 28 Mar, 2012 11 commits
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Jesse Barnes authored
Haven't seen this yet, but it doesn't hurt. Signed-off-by:
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Jesse Barnes authored
ValleyView has a new interrupt architecture; best to put it in a new set of functions. Also make sure the ring mask functions handle ValleyView. FIXME: fix flipping; need to enable interrupts and call prepare/finish Signed-off-by:
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Jesse Barnes authored
Signed-off-by:
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Jesse Barnes authored
ValleyView handles force wake differently than previous chipsets, so add a couple of new functions for it. But leave it disabled by default until we test it (need a chip with the Punit enabled first). Signed-off-by:
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Jesse Barnes authored
... and bind it right to the PCI id. Note that there are still a few things to fix here: - we need to move the tlb flush to a better place in drm/i915. - we need to check snoop support on vlv and implement it. Signed-off-by:
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Jesse Barnes authored
We need to flush the Gunit TLB when we update GTT PTEs on VLV, but the register for doing so is above the range we normally map. Map the whole register space to make sure we can get it. v2: only map the larger space on gen7+ (Daniel) Signed-off-by:
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Shobhit Kumar authored
HDMI register offsets are different in Valleyview. Add support for the same. v2: drop superfluous comments in HDMI init (Daniel) Signed-off-by:
Beeresh G <beeresh.g@intel.com> Signed-off-by:
Shobhit Kumar <shobhit.kumar@intel.com> Reviewed-by:
Vijay Purushothaman <vijay.a.purushothaman@intel.com> Reviewed-by:
Jesse Barnes <jesse.barnes@intel.com> Signed-off-by:
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Gajanan Bhat authored
This patch adds support for programming drain latency registers of Pondicherry memory arbiter of Valleyview. v2: clarify function names (Daniel) fix summary typo (Daniel) v3: add parens (Ben) make drain function return bool (Ben) Acked-by:Gajanan Bhat <gajanan.bhat@intel.com> Reviewed-by:
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Jesse Barnes authored
Set required clock gating and chicken bits on VLV. v2: set PIXEL_SUBSPAN_COLLECT_OPT_DISABLE too (Ben) move function below ivb version to pretend to be consistent (Ben) Reviewed-by: -
Jesse Barnes authored
ValleyView puts some display related registers like the PLL controls and dividers behind the DPIO bus. Add simple indirect register access routines to get to those registers. v2: move new wait_for macro to intel_drv.h (Ben) fix DPIO_PKT double write (Ben) add debugfs file Reviewed-by: -
Jesse Barnes authored
Add register definitions for the new VLV PLL bits. v2: remove unused bits & regs (Ben) Acked-by:
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