1. 20 Mar, 2006 12 commits
    • David S. Miller's avatar
      [SPARC64]: Dynamically grow TSB in response to RSS growth. · bd40791e
      David S. Miller authored
      As the RSS grows, grow the TSB in order to reduce the likelyhood
      of hash collisions and thus poor hit rates in the TSB.
      
      This definitely needs some serious tuning.
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      bd40791e
    • David S. Miller's avatar
      [SPARC64]: Add infrastructure for dynamic TSB sizing. · 98c5584c
      David S. Miller authored
      This also cleans up tsb_context_switch().  The assembler
      routine is now __tsb_context_switch() and the former is
      an inline function that picks out the bits from the mm_struct
      and passes it into the assembler code as arguments.
      
      setup_tsb_parms() computes the locked TLB entry to map the
      TSB.  Later when we support using the physical address quad
      load instructions of Cheetah+ and later, we'll simply use
      the physical address for the TSB register value and set
      the map virtual and PTE both to zero.
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      98c5584c
    • David S. Miller's avatar
      [SPARC64]: TSB refinements. · 09f94287
      David S. Miller authored
      Move {init_new,destroy}_context() out of line.
      
      Do not put huge pages into the TSB, only base page size translations.
      There are some clever things we could do here, but for now let's be
      correct instead of fancy.
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      09f94287
    • David S. Miller's avatar
      [SPARC64]: Elminate all usage of hard-coded trap globals. · 56fb4df6
      David S. Miller authored
      UltraSPARC has special sets of global registers which are switched to
      for certain trap types.  There is one set for MMU related traps, one
      set of Interrupt Vector processing, and another set (called the
      Alternate globals) for all other trap types.
      
      For what seems like forever we've hard coded the values in some of
      these trap registers.  Some examples include:
      
      1) Interrupt Vector global %g6 holds current processors interrupt
         work struct where received interrupts are managed for IRQ handler
         dispatch.
      
      2) MMU global %g7 holds the base of the page tables of the currently
         active address space.
      
      3) Alternate global %g6 held the current_thread_info() value.
      
      Such hardcoding has resulted in some serious issues in many areas.
      There are some code sequences where having another register available
      would help clean up the implementation.  Taking traps such as
      cross-calls from the OBP firmware requires some trick code sequences
      wherein we have to save away and restore all of the special sets of
      global registers when we enter/exit OBP.
      
      We were also using the IMMU TSB register on SMP to hold the per-cpu
      area base address, which doesn't work any longer now that we actually
      use the TSB facility of the cpu.
      
      The implementation is pretty straight forward.  One tricky bit is
      getting the current processor ID as that is different on different cpu
      variants.  We use a stub with a fancy calling convention which we
      patch at boot time.  The calling convention is that the stub is
      branched to and the (PC - 4) to return to is in register %g1.  The cpu
      number is left in %g6.  This stub can be invoked by using the
      __GET_CPUID macro.
      
      We use an array of per-cpu trap state to store the current thread and
      physical address of the current address space's page tables.  The
      TRAP_LOAD_THREAD_REG loads %g6 with the current thread from this
      table, it uses __GET_CPUID and also clobbers %g1.
      
      TRAP_LOAD_IRQ_WORK is used by the interrupt vector processing to load
      the current processor's IRQ software state into %g6.  It also uses
      __GET_CPUID and clobbers %g1.
      
      Finally, TRAP_LOAD_PGD_PHYS loads the physical address base of the
      current address space's page tables into %g7, it clobbers %g1 and uses
      __GET_CPUID.
      
      Many refinements are possible, as well as some tuning, with this stuff
      in place.
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      56fb4df6
    • David S. Miller's avatar
      [SPARC64]: Kill pgtable quicklists and use SLAB. · 3c936465
      David S. Miller authored
      Taking a nod from the powerpc port.
      
      With the per-cpu caching of both the page allocator and SLAB, the
      pgtable quicklist scheme becomes relatively silly and primitive.
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      3c936465
    • David S. Miller's avatar
      [SPARC64]: No need to D-cache color page tables any longer. · 05e28f9d
      David S. Miller authored
      Unlike the virtual page tables, the new TSB scheme does not
      require this ugly hack.
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      05e28f9d
    • David S. Miller's avatar
      [SPARC64]: Move away from virtual page tables, part 1. · 74bf4312
      David S. Miller authored
      We now use the TSB hardware assist features of the UltraSPARC
      MMUs.
      
      SMP is currently knowingly broken, we need to find another place
      to store the per-cpu base pointers.  We hid them away in the TSB
      base register, and that obviously will not work any more :-)
      
      Another known broken case is non-8KB base page size.
      
      Also noticed that flush_tlb_all() is not referenced anywhere, only
      the internal __flush_tlb_all() (local cpu only) is used by the
      sparc64 port, so we can get rid of flush_tlb_all().
      
      The kernel gets it's own 8KB TSB (swapper_tsb) and each address space
      gets it's own private 8K TSB.  Later we can add code to dynamically
      increase the size of per-process TSB as the RSS grows.  An 8KB TSB is
      good enough for up to about a 4MB RSS, after which the TSB starts to
      incur many capacity and conflict misses.
      
      We even accumulate OBP translations into the kernel TSB.
      
      Another area for refinement is large page size support.  We could use
      a secondary address space TSB to handle those.
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      74bf4312
    • Eric Sesterhenn's avatar
      [SPARC]: BUG_ON() Conversion in arch/sparc/kernel/ioport.c · 30d4d1ff
      Eric Sesterhenn authored
      this changes if() BUG(); constructs to BUG_ON() which is
      cleaner and can better optimized away
      Signed-off-by: default avatarEric Sesterhenn <snakebyte@gmx.de>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      30d4d1ff
    • Bernhard R Link's avatar
      [SPARC64]: fix sparc_floppy_irq's auxio_register reseting · 94bbc176
      Bernhard R Link authored
      The patch "[SPARC64]: Get rid of fast IRQ feature"
      moved the the code from arch/sparc64/kernel/entry.S:
            lduba           [%g7] ASI_PHYS_BYPASS_EC_E, %g5
            or              %g5, AUXIO_AUX1_FTCNT, %g5
            stba            %g5, [%g7] ASI_PHYS_BYPASS_EC_E
            andn            %g5, AUXIO_AUX1_FTCNT, %g5
            stba            %g5, [%g7] ASI_PHYS_BYPASS_EC_E
      to arch/sparc64/kernel/irq.c:
                    val = readb(auxio_register);
                    val |= AUXIO_AUX1_FTCNT;
                    writeb(val, auxio_register);
                    val &= AUXIO_AUX1_FTCNT;
                    writeb(val, auxio_register);
      This looks like it it missing a bitwise not, which is reintroduced
      by this patch.
      
      Due to lack of a floppy device, I could not test it, but it looks
      evident.
      Signed-off-by: default avatarBernhard R Link <brlink@debian.org>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      94bbc176
    • Linus Torvalds's avatar
      Linux 2.6.16 · 7705a879
      Linus Torvalds authored
      7705a879
    • Andrea Arcangeli's avatar
      [PATCH] Remove obsolete CREDITS address · 2be1aaf9
      Andrea Arcangeli authored
      This address is going to be obsolete, so I should update it.
      2be1aaf9
    • Linus Torvalds's avatar
      Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus · 46571909
      Linus Torvalds authored
      * 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus:
        [MIPS] SB1: Check for -mno-sched-prolog if building corelis debug kernel.
        [MIPS] Sibyte: Fix race in sb1250_gettimeoffset().
        [MIPS] Sibyte: Fix interrupt timer off by one bug.
        [MIPS] Sibyte: Fix M_SCD_TIMER_INIT and M_SCD_TIMER_CNT wrong field width.
        [MIPS] Protect more of timer_interrupt() by xtime_lock.
        [MIPS] Work around bad code generation for <asm/io.h>.
        [MIPS] Simple patch to power off DBAU1200
        [MIPS] Fix DBAu1550 software power off.
        [MIPS] local_r4k_flush_cache_page fix
        [MIPS] SB1: Fix interrupt disable hazard.
        [MIPS] Get rid of the IP22-specific code in arclib.
        Update MAINTAINERS entry for MIPS.
      46571909
  2. 19 Mar, 2006 2 commits
    • Michael Chan's avatar
      [TG3]: 40-bit DMA workaround part 2 · 4a29cc2e
      Michael Chan authored
      The 40-bit DMA workaround recently implemented for 5714, 5715, and
      5780 needs to be expanded because there may be other tg3 devices
      behind the EPB Express to PCIX bridge in the 5780 class device.
      
      For example, some 4-port card or mother board designs have 5704 behind
      the 5714.
      
      All devices behind the EPB require the 40-bit DMA workaround.
      
      Thanks to Chris Elmquist again for reporting the problem and testing
      the patch.
      Signed-off-by: default avatarMichael Chan <mchan@broadcom.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      4a29cc2e
    • Ralf Baechle DL5RB's avatar
      [AX.25]: Fix potencial memory hole. · c7c694d1
      Ralf Baechle DL5RB authored
      If the AX.25 dialect chosen by the sysadmin is set to DAMA master / 3
      (or DAMA slave / 2, if CONFIG_AX25_DAMA_SLAVE=n) ax25_kick() will fall
      through the switch statement without calling ax25_send_iframe() or any
      other function that would eventually free skbn thus leaking the packet.
      
      Fix by restricting the sysctl inferface to allow only actually supported
      AX.25 dialects.
      
      The system administration mistake needed for this to happen is rather
      unlikely, so this is an uncritical hole.
      
      Coverity #651.
      Signed-off-by: default avatarRalf Baechle DL5RB <ralf@linux-mips.org>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      c7c694d1
  3. 18 Mar, 2006 16 commits
  4. 17 Mar, 2006 10 commits