- 06 May, 2019 1 commit
-
-
Aaron Liu authored
In amdgpu_atif_handler, when hotplug event received, remove ATPX_DGPU_REQ_POWER_FOR_DISPLAYS check. This bit's check will cause missing system resume. Signed-off-by:
Aaron Liu <aaron.liu@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
-
- 03 May, 2019 1 commit
-
-
git://people.freedesktop.org/~agd5f/linuxDave Airlie authored
- SR-IOV fixes - Raven flickering fix - Misc spelling fixes - Vega20 power fixes - Freesync improvements - DC fixes Signed-off-by:
Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexdeucher@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190502193020.3562-1-alexander.deucher@amd.com
-
- 02 May, 2019 5 commits
-
-
Dave Airlie authored
Merge tag 'drm-intel-next-fixes-2019-05-02' of git://anongit.freedesktop.org/drm/drm-intel into drm-next - Whitelist a register to avoid media driver from hanging Signed-off-by:
-
Lionel Landwerlin authored
Unfortunately userspace users of this API cannot be publicly disclosed yet. This commit effectively disables timeline syncobj ioctls for all drivers. Each driver wishing to support this feature will need to expose DRIVER_SYNCOBJ_TIMELINE. v2: Add uAPI capability check (Christian) Signed-off-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Christian König <christian.koenig@amd.com> (v1) Cc: Dave Airlie <airlied@redhat.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Christian König <christian.koenig@amd.com> Cc: Chunming Zhou <david1.zhou@amd.com> Reviewed-by:
Chunming Zhou <david1.zhou@amd.com> Signed-off-by:
-
Lionel Landwerlin authored
We've been somewhat inconsistent when adding the new ioctl and returned ENODEV instead of EOPNOTSUPPORTED upon failing the syncobj capibility. Signed-off-by:
-
Dave Airlie authored
Merge tag 'drm-intel-next-fixes-2019-04-30' of git://anongit.freedesktop.org/drm/drm-intel into drm-next - Fix to Icelake CSC losing blue channel Signed-off-by:
-
Dave Airlie authored
Merge tag 'drm-misc-next-fixes-2019-05-01' of git://anongit.freedesktop.org/drm/drm-misc into drm-next core: restore drm mmap_range size back to 1TB (Philip) sphinx: squash warning (Sean) Cc: Philip Yang <Philip.Yang@amd.com> Cc: Sean Paul <seanpaul@chromium.org> Signed-off-by:
-
- 01 May, 2019 9 commits
-
-
git://github.com/skeggsb/linuxDave Airlie authored
No major changes ready for this round, but a few misc fixes instead. Signed-off-by:
-
Tobias Klausmann authored
On a failed resume we may experience unrecoverable errors. Plumb the error code through to actually let the driver fail. On a reverse-prime setup this helps the drm subsystem to at least recover the integrated gpu. This can especially happen with secboot timing out, leaving the hardware in a non-functioning state. Signed-off-by:
Tobias Klausmann <tobias.johannes.klausmann@mni.thm.de> Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
-
Colin Ian King authored
There is a spelling mistake in a nvkm_debug message. Fix it. Signed-off-by:
Colin Ian King <colin.king@canonical.com> Reviewed-by:
Mukesh Ojha <mojha@codeaurora.org> Signed-off-by:
-
Lyude Paul authored
For a while, we've had the problem of i2c bus access not grabbing a runtime PM ref when it's being used in userspace by i2c-dev, resulting in nouveau spamming the kernel log with errors if anything attempts to access the i2c bus while the GPU is in runtime suspend. An example: [ 130.078386] nouveau 0000:01:00.0: i2c: aux 000d: begin idle timeout ffffffff Since the GPU is in runtime suspend, the MMIO region that the i2c bus is on isn't accessible. On x86, the standard behavior for accessing an unavailable MMIO region is to just return ~0. Except, that turned out to be a lie. While computers with a clean concious will return ~0 in this scenario, some machines will actually completely hang a CPU on certian bad MMIO accesses. This was witnessed with someone's Lenovo ThinkPad P50, where sensors-detect attempting to access the i2c bus while the GPU was suspended would result in a CPU hang: CPU: 5 PID: 12438 Comm: sensors-detect Not tainted 5.0.0-0.rc4.git3.1.fc30.x86_64 #1 Hardware name: LENOVO 20EQS64N17/20EQS64N17, BIOS N1EET74W (1.47 ) 11/21/2017 RIP: 0010:ioread32+0x2b/0x30 Code: 81 ff ff ff 03 00 77 20 48 81 ff 00 00 01 00 76 05 0f b7 d7 ed c3 48 c7 c6 e1 0c 36 96 e8 2d ff ff ff b8 ff ff ff ff c3 8b 07 <c3> 0f 1f 40 00 49 89 f0 48 81 fe ff ff 03 00 76 04 40 88 3e c3 48 RSP: 0018:ffffaac3c5007b48 EFLAGS: 00000292 ORIG_RAX: ffffffffffffff13 RAX: 0000000001111000 RBX: 0000000001111000 RCX: 0000043017a97186 RDX: 0000000000000aaa RSI: 0000000000000005 RDI: ffffaac3c400e4e4 RBP: ffff9e6443902c00 R08: ffffaac3c400e4e4 R09: ffffaac3c5007be7 R10: 0000000000000004 R11: 0000000000000001 R12: ffff9e6445dd0000 R13: 000000000000e4e4 R14: 00000000000003c4 R15: 0000000000000000 FS: 00007f253155a740(0000) GS:ffff9e644f600000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 00005630d1500358 CR3: 0000000417c44006 CR4: 00000000003606e0 DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 Call Trace: g94_i2c_aux_xfer+0x326/0x850 [nouveau] nvkm_i2c_aux_i2c_xfer+0x9e/0x140 [nouveau] __i2c_transfer+0x14b/0x620 i2c_smbus_xfer_emulated+0x159/0x680 ? _raw_spin_unlock_irqrestore+0x1/0x60 ? rt_mutex_slowlock.constprop.0+0x13d/0x1e0 ? __lock_is_held+0x59/0xa0 __i2c_smbus_xfer+0x138/0x5a0 i2c_smbus_xfer+0x4f/0x80 i2cdev_ioctl_smbus+0x162/0x2d0 [i2c_dev] i2cdev_ioctl+0x1db/0x2c0 [i2c_dev] do_vfs_ioctl+0x408/0x750 ksys_ioctl+0x5e/0x90 __x64_sys_ioctl+0x16/0x20 do_syscall_64+0x60/0x1e0 entry_SYSCALL_64_after_hwframe+0x49/0xbe RIP: 0033:0x7f25317f546b Code: 0f 1e fa 48 8b 05 1d da 0c 00 64 c7 00 26 00 00 00 48 c7 c0 ff ff ff ff c3 66 0f 1f 44 00 00 f3 0f 1e fa b8 10 00 00 00 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d ed d9 0c 00 f7 d8 64 89 01 48 RSP: 002b:00007ffc88caab68 EFLAGS: 00000246 ORIG_RAX: 0000000000000010 RAX: ffffffffffffffda RBX: 00005630d0fe7260 RCX: 00007f25317f546b RDX: 00005630d1598e80 RSI: 0000000000000720 RDI: 0000000000000003 RBP: 00005630d155b968 R08: 0000000000000001 R09: 00005630d15a1da0 R10: 0000000000000070 R11: 0000000000000246 R12: 00005630d1598e80 R13: 00005630d12f3d28 R14: 0000000000000720 R15: 00005630d12f3ce0 watchdog: BUG: soft lockup - CPU#5 stuck for 23s! [sensors-detect:12438] Yikes! While I wanted to try to make it so that accessing an i2c bus on nouveau would wake up the GPU as needed, airlied pointed out that pretty much any usecase for userspace accessing an i2c bus on a GPU (mainly for the DDC brightness control that some displays have) is going to only be useful while there's at least one display enabled on the GPU anyway, and the GPU never sleeps while there's displays running. Since teaching the i2c bus to wake up the GPU on userspace accesses is a good deal more difficult than it might seem, mostly due to the fact that we have to use the i2c bus during runtime resume of the GPU, we instead opt for the easiest solution: don't let userspace access i2c busses on the GPU at all while it's in runtime suspend. Changes since v1: * Also disable i2c busses that run over DP AUX Signed-off-by:
Lyude Paul <lyude@redhat.com> Cc: stable@vger.kernel.org Signed-off-by:
-
Bjorn Helgaas authored
Commit 3a6536c5 ("drm/nouveau: Intercept ACPI_VIDEO_NOTIFY_PROBE") added a definition of ACPI_VIDEO_NOTIFY_PROBE because <acpi/video.h> didn't supply one. Later, commit eff4a751 ("ACPI / video: Move ACPI_VIDEO_NOTIFY_* defines to acpi/video.h") moved ACPI_VIDEO_NOTIFY_PROBE and other definitions to <acpi/video.h>, so the copy in nouveau_display.c is now unnecessary. Remove the unnecessary definition from nouveau_display.c. Signed-off-by:
Bjorn Helgaas <bhelgaas@google.com> CC: Hans de Goede <hdegoede@redhat.com> Acked-by:
Hans de Goede <hdegoede@redhat.com> Signed-off-by:
-
Jon Derrick authored
If the BAR initialization failed it may leave the vmm structure in an unitialized state, leading to a null-pointer-dereference when the vmm is dereferenced during teardown. Signed-off-by:
Jon Derrick <jonathan.derrick@intel.com> Signed-off-by:
-
Jon Derrick authored
If the BAR is zero size, it indicates it was never successfully mapped. Ensure that the BAR is valid during initialization before attempting to use it. Signed-off-by:
-
Jon Derrick authored
If the BAR is zero size, it indicates it was never successfully mapped. Ensure that the BAR is valid during initialization before attempting to use it. Signed-off-by:
-
Jon Derrick authored
Check bar1's new vmm creation return value for errors. Signed-off-by:
-
- 30 Apr, 2019 1 commit
-
-
Tvrtko Ursulin authored
WaEnableStateCacheRedirectToCS context workaround configures the L3 cache to benefit 3d workloads but media has different requirements. Remove the workaround and whitelist the register to allow any userspace configure the behaviour to their liking. v2: * Remove the workaround apart from adding the whitelist. Signed-off-by:
Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Cc: kevin.ma@intel.com Cc: xiaogang.li@intel.com Acked-by:
Anuj Phogat <anuj.phogat@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190418100634.984-1-tvrtko.ursulin@linux.intel.com Fixes: f63c7b48 ("drm/i915/icl: WaEnableStateCacheRedirectToCS") Reviewed-by:
Joonas Lahtinen <joonas.lahtinen@linux.intel.com> [tursulin: Anuj reported no GPU hangs or performance regressions with old Mesa on patched kernel.] (cherry picked from commit 0fc2273b) Signed-off-by:
-
- 29 Apr, 2019 21 commits
-
-
Evan Quan authored
Power down the engine also along with disabling its DPM functionality. Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
-
Evan Quan authored
SMU will use this interface to power down the VCE engine. Signed-off-by:
-
Mario Kleiner authored
Pre-DCE12 needs special treatment for BTR / low framerate compensation for more stable behaviour: According to comments in the code and some testing on DCE-8 and DCE-11, DCE-11 and earlier only apply VTOTAL_MIN/MAX programming with a lag of one frame, so the special BTR hw programming for intermediate fixed duration frames must be done inside the current frame at flip submission in atomic commit tail, ie. one vblank earlier, and the fixed refresh intermediate frame mode must be also terminated one vblank earlier on pre-DCE12 display engines. To achieve proper termination on < DCE-12 shift the point when the switch-back from fixed vblank duration to variable vblank duration happens from the start of VBLANK (vblank irq, as done on DCE-12+) to back-porch or end of VBLANK (handled by vupdate irq handler). We must leave the switch-back code inside VBLANK irq for DCE12+, as before. Doing this, we get much better behaviour of BTR for up-sweeps, ie. going from short to long frame durations (~high to low fps) and for constant framerate flips, as tested on DCE-8 and DCE-11. Behaviour is still not quite as good as on DCN-1 though. On down-sweeps, going from long to short frame durations (low fps to high fps) < DCE-12 is a little bit improved, although by far not as much as for up-sweeps and constant fps. v2: Fix some wrong locking, as pointed out by Nicholas. v3: Simplify if-condition in vupdate-irq - nit by Nicholas. Signed-off-by:
Mario Kleiner <mario.kleiner.de@gmail.com> Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by:
-
Mario Kleiner authored
The comparison of inserted_frame_duration_in_us against a duration calculated from max_refresh_in_uhz is both wrong in its math and not needed, as the min_duration_in_us value is already cached in in_out_vrr for reuse. No need to recalculate it wrongly at each invocation. Signed-off-by:
-
Nicholas Kazlauskas authored
RGB565 support isn't restricted to just the primary plane in DC, so also expose support for it on overlays. Signed-off-by:
David Francis <david.francis@amd.com> Signed-off-by:
-
Nicholas Kazlauskas authored
[Why] Originally we did the amdgpu_dm_handle_vrr_transition call before interrupts were enabled. After the interrupt toggling logic was moved around for support enabling CRTCs with no primary planes active this was no longer being called in the case where there wasn't a modeset. This fixes failures in igt@kms_vrr@* with error "Timed out: Waiting for vblank event". [How] Shift them back into the loop that always ran before interrupts were enabled. Pull out the logic that updated VRR state into the same loop since there's no reason these need to be split. In the case where we're going from VRR off, no planes to VRR on, some active planes we'll still be covered for having the VRR vupdate handler enabled - vblank will be re-enabled at this point, it will see that VRR is active and set the vupdate interrupt on there. Signed-off-by:
Leo Li <sunpeng.li@amd.com> Signed-off-by:
-
John Barberiz authored
Refactor dp vendor parsing int to a new function, and call it before get_active_converter_info(). Also, add a flag to skip parsing of Display ID 2.0. Some devices fail on readind DID2, but we shouldn't fail EDID read because of it. Add this flag to facilitate the logic. Signed-off-by:
John Barberiz <John.Barberiz@amd.com> Reviewed-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
-
Charlene Liu authored
Different HW will need to init HUBP differently. For now, add a vtable entry, and hook a NO-OP for DCN1. In addition, future HW will need to access the HUBPREQ_DEBUG register for hubp_init. Add it to the reg list. Signed-off-by:
Charlene Liu <charlene.liu@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
-
Eric Yang authored
[Why] The new interface now replaces the old interface for all known configurations. Signed-off-by:
Eric Yang <Eric.Yang2@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
-
Thomas Lim authored
[Why] Due to the generic introduction of seamless boot, the display is no longer blanked upon boot. However, this causes corruption on some systems that does not lock the memory in the non-secure boot case, resulting in brief corruption on boot due to garbage being written into the frame buffer. [How] Add a flag, read during DC init, to determine whether display should be blanked on boot. Default to true. Signed-off-by:
Thomas Lim <Thomas.Lim@amd.com> Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
-
Yongqiang Sun authored
* Replace certain register writes with register sets that overwrites the the entire register, instead of only a field within the register. * Add program_watermarks() entry to hubbub vtable. Hook it up to existing functions that program watermarks. * Add additional watermark registers. Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
-
Nicholas Kazlauskas authored
[Why] Many userspace applications (and IGT) seem to expect that most drivers can keep a CRTC active and enabled if there are no primary or overlay planes. DC is setup to handle this but only in the case where there are absolutely no planes on the CRTC - no primary, cursor, or overlay. [How] Add a check to reject commits that have cursor planes enabled and nothing else on CRTCs since we can't handle that. The new helper does_crtc_have_active_cursor is used for this. In atomic commit tail, we need to let DC know that there are zero planes enabled when doing stream updates to let it disable and blank pipes as appropriate. Signed-off-by:
-
Nicholas Kazlauskas authored
[Why] When disabling all the pipes for a CRTC the page-flip interrupt also gets disabled on Raven. We can't re-enable the page-flip interrupt unless we give DC at least one active DC plane. We currently enable interrupts after the call to dc_commit_state since there's currently no valid sequence that should disable all the planes or re-enable planes for a CRTC without first going through dc_commit_state. If we were to allow for a CRTC to be enabled with no primary plane this would not be the case - the call to dc_commit_updates_for_stream would enable the planes when going from zero to at least one active plane, but manage_dm_interrupts would have been called too early. This results in a page-flip timeout on any subsequent commits since we think the page-flip are now enabled when they're actually disabled. We need to enable interrupts after the call to dc_commit_updates_for_stream. [How] Split enabling interrupts into two passes. One pass before dc_commit_updates_for_stream and one after it. Shifting all the interrupts to be strictly below the call doesn't currently work even though it should in theory. We end up queuing off the vblank event to be handle by the flip handler before it's actually enabled in some cases, particularly: old_crtc_state->active = false -> new_crtc_state->active = true The framebuffer states haven't changed and we can technically still do a "pageflip" in this case and send back the event. Signed-off-by:
-
Nicholas Kazlauskas authored
[Why] We only currently drop the vblank reference when the stream is being removed from the context. We should be dropping it whenever we disable interrupts and reaquiring it after we re-enable them. We also never get the extra reference correctly when re-enabling interrupts, since grabbing the reference has the following condition: if (!crtc_state->crc_enabled && enable) drm_crtc_vblank_get(crtc); This means that crc_enabled must be *false* in order to grab the extra reference. [How] Always drop the ref whenever we're disabling interrupts. Only disable CRC capture when the stream is being removed. Always grab the ref by setting dm_new_crtc_state->crc_enabled = false before the call to re-enable CRC capture. Signed-off-by: -
Nicholas Kazlauskas authored
[Why] We can't do cursor programming after the planes have been disabled since there won't be any pipes - leading to lock warnings and the wrong cursor state being left in the registers. When we re-enable the planes after the previous cursor state will also remain if we don't have a cursor plane. [How] If we're disabling the planes then do the cursor programming first. If we're not disabling the planes then do the cursor programming after. Introduce the amdgpu_dm_commit_cursors helper to avoid code duplication for both of these cases. Signed-off-by:
-
Nicholas Kazlauskas authored
[Why] The vblank and pageflip interrupts should only be enabled for a CRTC that's enabled and has active planes. The current logic takes care of this, but isn't setup to handle the case where the active plane count goes to zero but the stream remains enabled. We currently block this case since we don't allow commits that enable a CRTC with no active planes, but shouldn't be any reason we can't support this from a hardware perspective and many userspace applications expect to be able to do it (like IGT). [How] The count_crtc_active_planes function fills in the number of "active_planes" on the dm_crtc_state. This should be the same as DC's plane_count on the stream_status but easier to access since we don't need to lock the private atomic state with the DC context. Add the "interrupts_enabled" flag to the dm_crtc_state and set it based on whether the stream exists and if there are active planes on the stream. Update the disable and enable logic to make use of this new flag. There shouldn't be any functional change (yet) with this patch. Signed-off-by:
-
Wentao Lou authored
amdgpu_sriov_vf would return 0x0 or 0x4 to indicate if sriov. but F32_POLL_ENABLE need 0x0 or 0x1 to determine if enabled. set 0x4 into F32_POLL_ENABLE would make SDMA0_GFX_RB_WPTR_POLL_CNTL not working. Signed-off-by:
Wentao Lou <Wentao.Lou@amd.com> Reviewed-by:
-
Evan Quan authored
Update Vega20 sdma golden settings. Signed-off-by:
-
hersen wu authored
[WHY] clock unit mis-match between caller DC and SMU interface. dc pass lock in mhz. the same unit as smu. no covert is needed. [HOW] remove covert_10k_to_mhz in smu interface this fixes corruption issue with 4k @60 display and stutter mode enable Reviewed-by:Kenneth Feng <kenneth.feng@amd.com> Signed-off-by:
hersen wu <hersenxs.wu@amd.com> Signed-off-by:
-
Colin Ian King authored
Currently an allocation is being made but the allocation failure check is being performed on another pointer. Fix this by checking the correct pointer. Also use the normal kernel idiom for null pointer checks. Addresses-Coverity: ("Resource leak") Fixes: 43e3ac83 ("drm/amd/display: Add function to copy DC streams") Signed-off-by: -
Ville Syrjälä authored
When I refactored the code into its own function I accidentally misplaced the <<16 shifts for some of the registers causing us to lose the blue channel entirely. We should really find a way to test this... Cc: Uma Shankar <uma.shankar@intel.com> Fixes: d2c19b06 ("drm/i915: Clean up ilk/icl pipe/output CSC programming") Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190425192419.24931-1-ville.syrjala@linux.intel.comReviewed-by:
Swati Sharma <swati2.sharma@intel.com> (cherry picked from commit d428ca17) Signed-off-by:
-
- 26 Apr, 2019 2 commits
-
-
Dave Airlie authored
Merge tag 'drm-intel-next-fixes-2019-04-25' of git://anongit.freedesktop.org/drm/drm-intel into drm-next - Use after free fix during GEM_CREATE when reporting back object size - Icelake DP register programming order fix Signed-off-by:
-
Dave Airlie authored
Merge tag 'drm-misc-next-fixes-2019-04-24' of git://anongit.freedesktop.org/drm/drm-misc into drm-next - fb_helper: Fix NULL deref in legacy drivers (Noralf) - leases: Ensure lessees can't connect to objects outside their perview (Daniel) - leases: Enforce that lessees hold the lease for implicitly set planes (Daniel) - leases: A few non-functional cleanups (Daniel) Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Noralf Trønnes <noralf@tronnes.org> Signed-off-by:
-
