- 03 Jun, 2010 8 commits
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Tiago Vignatti authored
Signed-off-by:
Tiago Vignatti <tiago.vignatti@nokia.com> Cc: Henry Zhao <Henry.Zhao@Sun.COM> Signed-off-by:
Dave Airlie <airlied@redhat.com>
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Tiago Vignatti authored
We want to be able to use CONFIG_DYNAMIC_DEBUG in arbiter code, switch the few existing pr_devel() calls to pr_debug(). Also, add one more debug information regarding decoding count. Signed-off-by:
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Nicolas Kaiser authored
A few typos in the DRM Developer's Guide. Signed-off-by:
Nicolas Kaiser <nikai@nikai.net> Acked-by:
Jesse Barnes <jesse.barnes@intel.com> Signed-off-by:
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Alex Deucher authored
- Enable GPIO voltage for non pm modes as well so resetting the default voltage works. Signed-off-by:
Alex Deucher <alexdeucher@gmail.com> Signed-off-by:
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Alex Deucher authored
- wait for vbl for both profile and dynpm - unify profile and dynpm code paths more - call pm_misc before of after clocks to make sure voltage is changed in the proper order. Signed-off-by:
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Alex Deucher authored
The default power state does not always match the default clocks and voltage for a particular card. The information in the firmware info table is correct and should be used in preference to the info the default power state. Signed-off-by:
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Alex Deucher authored
I missed these in the r6xx commit. Signed-off-by:
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Alex Deucher authored
- This enables voltage adjustment on r6xx+ and certain r5xx asics. - Voltage drop support is already available for most r1xx-r5xx asics. V2: endian fix for voltage table. Signed-off-by:
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- 01 Jun, 2010 7 commits
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Alex Deucher authored
Advanced validation is not implemented yet. The mesa code that uses this will be released soon. Signed-off-by:
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Dave Airlie authored
* 'nouveau/for-airlied' of ../drm-nouveau-next: drm/nv50: cast IGP memory location to u64 before shifting drm/nv50: use alternate source of SOR_MODE_CTRL for DP hack drm/nouveau: fix dual-link displays when plugged into single-link outputs drm/nv50: obey dcb->duallink_possible drm/nv50: fix duallink_possible calculation for DCB 4.0 cards drm/nouveau: don't execute INIT_GPIO unless we're really running the table drm/nv40: allow cold-booting of nv4x chipsets drm/nouveau: fix POST detection for certain chipsets drm/nouveau: Add getparam for current PTIMER time. drm/nouveau: allow cursor image and position to survive suspend
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Dave Airlie authored
* drm-switcheroo-fixes: drm/kms: disable/enable poll around switcheroo on/off drm/nouveau: fixup confusion over which handle the DSM is hanging off. drm/nouveau: attempt to get bios from ACPI v3
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Dave Airlie authored
* drm-vmware-fixes: drm/vmwgfx: Remove some leftover debug messages. drm/vmwgfx: Print warnings in kernel log about bo pinning that fails. drm/vmwgfx: Unpause overlay on update. drm/vmwgfx: Some modesetting cleanups and fixes. drm/vmwgfx: Don't use SVGA_REG_ENABLE in modesetting code. drm/vmwgfx: Remove duplicate member from struct vmw_legacy_display_unit. drm/vmwgfx: Reserve first part of VRAM for framebuffer. drm/vmwgfx: Support older hardware. drm/vmwgfx: Get connector status from detection function. drm/vmwgfx: Add kernel throttling support. Bump minor. drm/vmwgfx: Make sure to unpin old and pin new framebuffer. drm/vmwgfx: Fix single framebuffer detection. drm/vmwgfx: Assume larger framebuffer max size.
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Dave Airlie authored
Because we aren't in a suspend state the poll will still run when we have switcherooed a card off. Signed-off-by: -
Dave Airlie authored
This fixes the DSM setup correctly since vga switcheroo. Signed-off-by: -
Dave Airlie authored
Some of the laptops with the switchable graphics, seem to not post the secondary GPU at all, and we can't find a copy of the BIOS anywhere except in the ACPI rom retrieval. This adds support for ACPI ROM retrieval to nouveau. Signed-off-by:
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- 31 May, 2010 16 commits
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Ben Skeggs authored
Signed-off-by:Ben Skeggs <bskeggs@redhat.com>
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Thomas Hellstrom authored
Fix a number of typos misspellings and checkpatch.pl warnings. Replace "[ttm] " with TTM_PFX Signed-off-by:
Thomas Hellstrom <thellstrom@vmware.com> Signed-off-by:
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Thomas Hellstrom authored
This patch fixes a regression introduced with the pool page allocator in the event that there are no highmem pages (for example x86_64), in which case cached page allocation would fail. Tested with the vmwgfx driver on a 64-bit vm. Signed-off-by:
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Thomas Hellstrom authored
Signed-off-by:
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Jakob Bornecrantz authored
Signed-off-by:
Jakob Bornecrantz <jakob@vmware.com> Signed-off-by:
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Jakob Bornecrantz authored
The unpause codepath uses vmw_overlay_update() so we must unset the paused status. Signed-off-by:
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Jakob Bornecrantz authored
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Jakob Bornecrantz authored
We should not use SVGA_REG_ENABLE anywhere but in the fifo setup code, since it controls whether the device is active. Signed-off-by:
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Jakob Bornecrantz authored
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Thomas Hellstrom authored
The host may be touching this part of VRAM at modesetting, even if we never use it ourselves, since we blit screen updates from 3D surfaces. Make sure no DMA buffers are placed in this part of VRAM. V2: Fix an error check in vmw_surface_dmabuf_pin(). Signed-off-by:
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Jakob Bornecrantz authored
V2: Fix a couple of typos. Signed-off-by:
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Jakob Bornecrantz authored
Also make sure the ldu::active member is properly initialized. Part of fix by Michel Daenzer <daenzer@vmware.com>. Signed-off-by:
Michel Daenzer <daenzer@vmware.com> Signed-off-by:
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Thomas Hellstrom authored
The throttle_us member in the execbuf argument is now honored. If the member is 0, no waiting for lag will occur, which guarantees backwards compatibility with well-behaved clients. Signed-off-by:
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Jakob Bornecrantz authored
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Jakob Bornecrantz authored
V2: Fix a typo. Signed-off-by:
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Jakob Bornecrantz authored
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- 28 May, 2010 9 commits
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Dave Airlie authored
airlied -> brown paper bag. I blame Hi-5 or the Wiggles for lowering my IQ, move the fix inside some brackets instead of breaking everything in site. Cc: stable@kernel.org Signed-off-by: -
Ben Skeggs authored
Fixes module unload+reload on Dell M4500, where the "normal" registers get reset to 0. Signed-off-by: -
Ben Skeggs authored
When selecting the native mode for a display we weren't taking into account whether or not it was actually supported on that particular output. This patch modifies our native mode selection to run all modes through mode_valid() first. Signed-off-by: -
Ben Skeggs authored
It was once assumed that all G8x had dual-link TMDS everywhere, this isn't actually the case - especially considering passive DP->DVI converters and some HDMI connectors only support single-link. Signed-off-by: -
Ben Skeggs authored
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Ben Skeggs authored
This resulted in accidently switching off the eDP panel on certain laptops since the default state in the GPIO table was off. Fixes rh#582621 Signed-off-by: -
Ben Skeggs authored
Signed-off-by: -
Ben Skeggs authored
We totally fail at detecting un-POSTed chipsets prior to G80. This commit changes the pre-G80 POST detection to read the programmed horizontal total from CRTC 0, and assume the card isn't POSTed if it's 0. NVIDIA use some other heuristics more similar to what we do on G80, but I wasted quite a long time trying to figure out the exact specifics of what they do so we can try this for a bit instead. Signed-off-by: -
Marcin Kościelnicki authored
This will be useful for computing GPU-CPU latency, including GL_ARB_timer_query extension. Signed-off-by:
Marcin Kościelnicki <koriakin@0x04.net> Signed-off-by:
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