- 01 May, 2018 12 commits
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Felix Kuehling authored
Only accept interrupts from KFD VMIDs. Just checking for a PASID may not be enough because amdgpu started using PASIDs to map VM faults to processes. Warn if an IRQ doesn't have a valid PASID (indicating a firmware bug). Suggested-by:
Shaoyun Liu <Shaoyun.Liu@amd.com> Suggested-by:
Oak Zeng <Oak.Zeng@amd.com> Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by:
Oded Gabbay <oded.gabbay@gmail.com> Signed-off-by:
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Shaoyun Liu authored
HWS may hang in the middle of destroy queue, remove the queue from the process queue list so it won't be freed again in the future Signed-off-by:
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Ben Goz authored
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Ben Goz <ben.goz@amd.com> Reviewed-by:
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Felix Kuehling authored
The initialization is not necessary. amd-kfd-staging and ROCm releases have worked without it for two years. Signed-off-by:
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Felix Kuehling authored
It turns out that idr_for_each_entry is really slow compared to just iterating over the slots. Based on measurements the difference is estimated to be about a factor 64. That means using idr_for_each_entry is only worth it with very few allocated events. Signed-off-by:
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Yong Zhao authored
The problem happens on Raven and Carrizo. The context save handler should not clear the high bits of PC_HI before extracting the bits of IB_STS. The bug is not relevant to VEGA10 until we enable demand paging. Signed-off-by:
Jay Cornwall <Jay.Cornwall@amd.com> Signed-off-by:
Yong Zhao <yong.zhao@amd.com> Reviewed-by:
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Yong Zhao authored
Since the assembly code is inside "#if 0", it is ineffective. Despite that, during debugging, we need to change the assembly code, extract it into a separate file and compile the new file into hex values using sp3. That process also requires us to remove "#if 0" and modify lines starting with "#", so that sp3 can successfully compile the new file. With this change, all the above chore is no longer needed, and cwsr_trap_handler_gfx*.asm can be directly used by sp3 to generate its hex values. Signed-off-by:
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Felix Kuehling authored
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Philip Yang authored
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Philip Yang <Philip.Yang@amd.com> Reviewed-by:
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Jay Cornwall authored
MTYPE_NC_NV (0) marks scalar/vector L1 cache lines as non-volatile. Cache lines loaded through these apertures are intended to be invalidated before (and sometimes during) a dispatch. The non-volatile qualifier prevents these cache lines from being distinguished from those loaded through the private aperture. Use MTYPE_NC (1) instead on both Gfx7 and Gfx8. This allows the compiler to use the BUFFER_WBINVL1_VOL instruction and is a precursor to automatic per-dispatch scalar/vector L1 volatile invalidation. Signed-off-by:
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Jay Cornwall authored
Synchronization between context-saving wavefronts is achieved by sending a SAVEWAVE message to the SPI and then spin-waiting for a response. These spin-waiting wavefronts may inhibit the progress of other wavefronts in the context save handler, leading to the synchronization condition never being achieved. Before spin-waiting reduce the priority of each wavefront to guarantee foward progress in the others. Signed-off-by:
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Oak Zeng authored
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- 24 Apr, 2018 1 commit
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Dan Carpenter authored
args->n_devices is a u32 that comes from the user. The multiplication could overflow on 32 bit systems possibly leading to privilege escalation. Fixes: 5ec7e028 ("drm/amdkfd: Add ioctls for GPUVM memory management") Signed-off-by: Dan Carpenter dan.carpenter@oracle.com> Reviewed-by:
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- 10 Apr, 2018 5 commits
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Felix Kuehling authored
* Report 64-bit doorbells as HSA_CAP_DOORBELL_TYPE_2_0 in topology * Report cache information in topology (duplicates GFXv8 info for now) * Add device info for Vega10 support in KFD Raven is not enabled at this time as it needs additional changes in DQM to work with a single SDMA engine. Signed-off-by:
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welu authored
Report failure to enable atomics only on GPUs that require them. This allows GPUs that don't require atomics to function, but can benefit if they are available. This is the case for Vega10, which doesn't use atomics for basic functioning of the MEC, AQL and HWS microcode. So it can work without atomics. But shader programs can still use atomic instructions on systems that support PCIe atomics. Signed-off-by:
welu <Wei.Lu2@amd.com> Signed-off-by:
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Felix Kuehling authored
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Felix Kuehling authored
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Felix Kuehling authored
This condition was missed in a previous commit with the same title. Signed-off-by:
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- 09 Apr, 2018 1 commit
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Felix Kuehling authored
v2: Removed redundant 0x before %p. Signed-off-by:
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- 10 Apr, 2018 15 commits
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Felix Kuehling authored
kq->queue->properties.write_ptr is a GPU address which can'd be derefenced in the kernel. Use kq->wptr_kernel instead, which is the kernel CPU address of the same buffer. Signed-off-by:
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Felix Kuehling authored
Missed a spot in previous cleanup commit: Remove gotos that do not feature any common cleanup, and use gotos instead of repeating cleanup commands. According to kernel.org: "The goto statement comes in handy when a function exits from multiple locations and some common work such as cleanup has to be done. If there is no cleanup needed then just return directly." Signed-off-by:
Kent Russell <kent.russell@amd.com> Signed-off-by:
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Felix Kuehling authored
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Felix Kuehling authored
Signed-off-by:
John Bridgman <john.bridgman@amd.com> Signed-off-by:
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Felix Kuehling authored
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Felix Kuehling authored
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Felix Kuehling authored
This is in preparation for GFXv9 (Vega10) which uses incompatible PM4 packet formats from previous ASIC generations. Signed-off-by:
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Felix Kuehling authored
Allocate doorbells according to the doorbell routing information on SOC15 ASICs (Vega10 and later). On older ASICs we continue to use the queue_id as the doorbell ID to maintain compatibility with the Thunk. Signed-off-by:
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Harish Kasiviswanathan authored
Use bit-rotate for better clarity and remove _MASK from the #defines as these represent mmap types. Centralize all the parsing of the mmap offset in kfd_mmap and add device parameter to doorbell and reserved_mem map functions. Encode gpu_id into upper bits of vm_pgoff. This frees up the lower bits for encoding the the doorbell ID on Vega10. Signed-off-by:
Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by:
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Felix Kuehling authored
This prepares for GFXv9 (Vega10), which has 64-bit doorbells. Signed-off-by:
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Felix Kuehling authored
This is needed for Vega10 and later ASICs to let KFD know which doorbells can be used for SDMA and CP queues respectively. Signed-off-by:
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Felix Kuehling authored
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Felix Kuehling authored
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Felix Kuehling authored
This matches what the HWS firmware expects on GFXv9 chips. Signed-off-by:
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Felix Kuehling authored
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- 23 Mar, 2018 6 commits
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Felix Kuehling authored
This adds support for allocating, mapping, unmapping and freeing userptr BOs, and for handling MMU notifiers. v2: updated a comment Signed-off-by:
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Felix Kuehling authored
These interfaces allow KGD to stop and resume all GPU user mode queue access to a process address space. This is needed for handling MMU notifiers of userptrs mapped for GPU access in KFD VMs. Signed-off-by:
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Felix Kuehling authored
When an MMU notifier runs in memory reclaim context, it can deadlock trying to take locks that are already held in the thread causing the memory reclaim. The solution is to avoid memory reclaim while holding locks that are taken in MMU notifiers by using GFP_NOIO. This commit fixes memory allocations done while holding the dqm->lock which is needed in the MMU notifier (dqm->ops.evict_process_queues). Signed-off-by:
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Felix Kuehling authored
When an MMU notifier runs in memory reclaim context, it can deadlock trying to take locks that are already held in the thread causing the memory reclaim. The solution is to avoid memory reclaim while holding locks that are taken in MMU notifiers. This commit fixes kmalloc while holding rmn->lock by moving the call outside the lock. The GFX MMU notifier also locks reservation objects. I have no good solution for avoiding reclaim while holding reservation objects. The HSA MMU notifier will not lock any reservation objects. v2: Moved allocation outside lock instead of using GFP_NOIO Signed-off-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Felix Kuehling authored
This commit allows amdgpu_ttm_tt_get_user_pages to work in a worker thread rather than regular process context. This will be used when KFD userptr BOs are restored after an MMU-notifier eviction. v2: Manage task reference with get_task_struct/put_task_struct Signed-off-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Felix Kuehling authored
This commit adds the notion of MMU notifier types GFX and HSA. GFX continues to work like MMU notifiers did before. HSA adds support for KFD userptr BOs. The implementation of KFD userptr eviction is a stub for now. Signed-off-by:
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