- 06 Feb, 2019 33 commits
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James Smart authored
The XRI get/put lists were partitioned per hardware queue. However, the adapter rarely had sufficient resources to give a large number of resources per queue. As such, it became common for a cpu to encounter a lack of XRI resource and request the upper io stack to retry after returning a BUSY condition. This occurred even though other cpus were idle and not using their resources. Create as efficient a scheme as possible to move resources to the cpus that need them. Each cpu maintains a small private pool which it allocates from for io. There is a watermark that the cpu attempts to keep in the private pool. The private pool, when empty, pulls from a global pool from the cpu. When the cpu's global pool is empty it will pull from other cpu's global pool. As there many cpu global pools (1 per cpu or hardware queue count) and as each cpu selects what cpu to pull from at different rates and at different times, it creates a radomizing effect that minimizes the number of cpu's that will contend with each other when the steal XRI's from another cpu's global pool. On io completion, a cpu will push the XRI back on to its private pool. A watermark level is maintained for the private pool such that when it is exceeded it will move XRI's to the CPU global pool so that other cpu's may allocate them. On NVME, as heartbeat commands are critical to get placed on the wire, a single expedite pool is maintained. When a heartbeat is to be sent, it will allocate an XRI from the expedite pool rather than the normal cpu private/global pools. On any io completion, if a reduction in the expedite pools is seen, it will be replenished before the XRI is placed on the cpu private pool. Statistics are added to aid understanding the XRI levels on each cpu and their behaviors. Signed-off-by:
Dick Kennedy <dick.kennedy@broadcom.com> Signed-off-by:
James Smart <jsmart2021@gmail.com> Reviewed-by:
Hannes Reinecke <hare@suse.com> Signed-off-by:
Martin K. Petersen <martin.petersen@oracle.com>
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James Smart authored
Now that the lower half has much better per-cpu parallelization using the hardware queues, the SCSI MQ support needs to be tied into it. The involves the following mods: - Use the hardware queue info from the midlayer to help select the hardware queue to utilize. This required change to the get_scsi-buf_xxx routines. - Remove lpfc_sli4_scmd_to_wqidx_distr() routine. No longer needed. - Includes fix for SLI-3 that does not have multi queue parallelization. Signed-off-by:
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James Smart authored
SLI4 nvme functions are passing the SLI3 ring number when posting wqe to hardware. This should be indicating the hardware queue to use, not the ring number. Replace ring number with the hardware queue that should be used. Note: SCSI avoided this issue as it utilized an older lfpc_issue_iocb routine that properly adapts. Signed-off-by:
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James Smart authored
Many io statistics were being sampled and saved using adapter-based data structures. This was creating a lot of contention and cache thrashing in the I/O path. Move the statistics to the hardware queue data structures. Given the per-queue data structures, use of atomic types is lessened. Add new sysfs and debugfs stat routines to collate the per hardware queue values and report at an adapter level. Signed-off-by:
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James Smart authored
Similar to the io execution path that reports cpu context information, the debugfs routines for cpu information needs to be aligned with new hardware queue implementation. Convert debugfs cnd nvme cpucheck statistics to report information per Hardware Queue. Signed-off-by:
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James Smart authored
Both NVME and SCSI aborts are now processed off the CQ workqueue and do not generate events for the slowpath any more. Remove the unused event code. Signed-off-by:
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James Smart authored
Once the IO buff allocations were made shared, there was a single XRI buffer list shared by all hardware queues. A single list isn't great for performance when shared across the per-cpu hardware queues. Create a separate XRI IO buffer get/put list for each Hardware Queue. As SGLs and associated IO buffers get allocated/posted to the firmware; round robin their assignment across all available hardware Queues so that there is an equitable assignment. Modify SCSI and NVME IO submit code paths to use the Hardware Queue logic for XRI allocation. Add a debugfs interface to display hardware queue statistics Added new empty_io_bufs counter to track if a cpu runs out of XRIs. Replace common_ variables/names with io_ to make meanings clearer. Signed-off-by:
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James Smart authored
Currently, both nvme and fcp each have their own concept of an io_channel, which is a combination wq/cq and associated msix. Different cpus would share an io_channel. The driver is now moving to per-cpu wq/cq pairs and msix vectors. The driver will still use separate wq/cq pairs per protocol on each cpu, but the protocols will share the msix vector. Given the elimination of the nvme and fcp io channels, the module parameters will be removed. A new parameter, lpfc_hdw_queue is added which allows the wq/cq pair allocation per cpu to be overridden and allocated to lesser value. If lpfc_hdw_queue is zero, the number of pairs allocated will be based on the number of cpus. If non-zero, the parameter specifies the number of queues to allocate. At this time, the maximum non-zero value is 64. To manage this new paradigm, a new hardware queue structure is created to track queue activity and relationships. As MSIX vector allocation must be known before setting up the relationships, msix allocation now occurs before queue datastructures are allocated. If the number of vectors allocated is less than the desired hardware queues, the hardware queue counts will be reduced to the number of vectors Signed-off-by:
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James Smart authored
There is a extra queue and msix vector for expresslane. Now that the driver will be doing queues per cpu, this oddball queue is no longer needed. Expresslane will utilize the normal per-cpu queues. Updated debugfs sli4 queue output to go along with the change Signed-off-by:
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James Smart authored
Currently, both NVME and SCSI get their IO buffers from separate pools. XRI's are associated 1:1 with IO buffers, so XRI's are also split between protocols. Eliminate the independent pools and use a single pool. Each buffer structure now has a common section and a protocol section. Per protocol routines for SGL initialization are removed and replaced by common routines. Initialization of the buffers is only done on the common area. All other fields, which are protocol specific, are initialized when the buffer is allocated for use in the per-protocol allocation routine. In the past, the SCSI side allocated IO buffers as part of slave_alloc calls until the maximum XRIs for SCSI was reached. As all XRIs are now common and may be used for either protocol, allocation for everything is done as part of adapter initialization and the scsi side has no action in slave alloc. As XRI's are no longer split, the lpfc_xri_split module parameter is removed. Adapters based on SLI3 will continue to use the older scsi_buf_list_get/put routines. All SLI4 adapters utilize the new IO buffer scheme Signed-off-by:
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James Smart authored
lpfc_nvme_prep_io_cmd() checks for null pnode, but caller lpfc_nvme_fcp_io_submit() has already ensured it's non-null. Remove the pnode null check. Signed-off-by:
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James Smart authored
An hba-wide lock is taken in the nvme io completion routine. The lock covers null'ing of the nrport pointer in the cmd structure. The nrport member isn't necessary. After extracting the pointer from the command, the pointer was dereferenced to get the fc discovery node pointer. But the fc discovery node pointer is alrady in the command structure so the dereferrence was unnecessary. Eliminated the nrport structure member and its use, which also eliminates the port-wide lock. Signed-off-by:
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Himanshu Madhani authored
Signed-off-by:
Himanshu Madhani <hmadhani@marvell.com> Signed-off-by:
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Quinn Tran authored
This patch removes unnecessary code to handle RSCN, instead performs full scan everytime driver receives RSCN Fixes: d4f7a16a ("scsi: qla2xxx: Remove ASYNC GIDPN switch command") Cc: stable@vger.kernel.org #4.19 Signed-off-by:
Quinn Tran <qtran@marvell.com> Signed-off-by:
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Quinn Tran authored
For eh_bus_reset, driver is supposed to reset the link. Current option to reset the link is applicable to Loop only. This patch updates current FW option with the one that is applicable to all topologies. Signed-off-by:
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Sawan Chandak authored
When loop was made down explicitly due to cable pull, then for N2N toplogy, if FAWWPN BIT is enabled by user, then it would restore some default (garbage) value for Physical port WWPN, so this show garbage WWPN for the port. Fix is, to restore physical port WWPN, if it is fabric configuration. When loop is explicitly made down, and FAWWPN feature is enabled, then driver need to restore original flashed WWPN. Signed-off-by:
Sawan Chandak <schandak@marvell.com> Signed-off-by:
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Quinn Tran authored
This patch fixes memory leak by releasing DMA memory in case CT request and response allocation fails. Signed-off-by:
Quinn Tran <qtran@marvall.com> Signed-off-by:
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Giridhar Malavali authored
This patch fixes SRB allocation flag from GFP_KERNEL to GFP_ATOMIC, to prevent sleeping in IRQ context Signed-off-by:
Giridhar Malavali <gmalavali@marvell.com> Signed-off-by:
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Quinn Tran authored
This patch flushes del_work and free_work while sending NACK response for PRLI Signed-off-by:
Quinn Tran <quinn.tran@cavium.com> Signed-off-by:
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Quinn Tran authored
This patch allocates DMA memory to prevent NULL pointer access for ct_sns request while sending switch commands. Signed-off-by:
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Quinn Tran authored
On Transmit respond in target mode, if the chip is already reset or the session is already deleted, then advance the command to the free step. There is no need to abort the command, because the chip has already flushed it. Signed-off-by:
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Quinn Tran authored
On session cleanup, either an implicit LOGO or an implicit PRLO is used to flush IOs. If the flush command hit Queue Full condition, then it is dropped. This patch adds retry code to prevent command drop. Signed-off-by:
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Quinn Tran authored
Change default ZIO threshold to an optimized value. Signed-off-by:
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Quinn Tran authored
This patch provide call back functions to stop the chip and resume the chip if the PCI lower level driver wants to perform function level reset/FLR. Before the FLR, the chip will be stopped to turn off all DMA activity. After the FLR, the chip is reset to resume previous operation state. Signed-off-by:
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Himanshu Madhani authored
This patch fixes the issue where Dell-EMC Target will fail to discover LUNs if domain and area of port ID is not same as adapter's. Signed-off-by:
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Christoph Hellwig authored
Unused now, and another field in struct request bites the dust. Signed-off-by:
Christoph Hellwig <hch@lst.de> Acked-by:
Jens Axboe <axboe@kernel.dk> Signed-off-by:
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Christoph Hellwig authored
No users left. Signed-off-by:
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Christoph Hellwig authored
No more need in a blk-mq world where the scsi command and request are allocated together. Signed-off-by:
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Christoph Hellwig authored
No real need for bidi support once the OSD code is gone. Signed-off-by:
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Christoph Hellwig authored
Now that all the users are gone the SCSI OSD library can be removed as well. Signed-off-by:
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Christoph Hellwig authored
This was an example for using the SCSI OSD protocol, which we're trying to remove. Signed-off-by:
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Christoph Hellwig authored
We can just stash away the second request in struct bsg_job instead of using the block layer req->next_rq field, allowing for the eventual removal of the latter. Signed-off-by:
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Christoph Hellwig authored
Move all actual functionality into helpers, just leaving the dispatch in this function. Signed-off-by:
Benjamin Block <bblock@linux.ibm.com> Tested-by:
Avri Altman <avri.altman@wdc.com> Acked-by:
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- 05 Feb, 2019 7 commits
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Suganath Prabu S authored
Updated driver version to 27.102.00.00 from 27.101.00.00. Signed-off-by:
Suganath Prabu S <suganath-prabu.subramani@broadcom.com> Signed-off-by:
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Suganath Prabu S authored
Add Atlas PCIe Switch Management Port device PNPID, Vendor Id: 0x1000 device Id: 0x00B2 This device is based on MPI 2.6 spec and it exposes one SES device to accept management commands for the PCIe switch. Signed-off-by:
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Suganath Prabu S authored
Added device ID for NVMe Switch Adapter (Ambrosia). VID: 0x1000 DID: 0x02B1 Signed-off-by:
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Suganath Prabu S authored
MPI Endpoint is a PCIe switch based on MPI2. Renaming device ID macro from MPI2_MFGPAGE_DEVID_SAS2308_MPI_EP to MPI2_MFGPAGE_DEVID_SWITCH_MPI_EP. Signed-off-by:
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Shivasharan S authored
This patch adds support for the new DEVICE_LIST DCMD. Driver currently sends two separate DCMDs for getting the list of PDs and LDs that are exposed to host. The new DCMD provides a single interface to get a list of both PDs and LDs that are exposed to the host. Based on the list of target IDs that are returned by this DCMD, driver will add the devices (PD/LD) to SML. Driver will check for FW support for this new DCMD and based on the support will either send the new DCMD or will fall back to the earlier method of sending two separate DCMDs for PD and LD list. Signed-off-by:
Kashyap Desai <kashyap.desai@broadcom.com> Signed-off-by:
Shivasharan S <shivasharan.srikanteshwara@broadcom.com> Signed-off-by:
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Shivasharan S authored
In preparation of adding support for the DEVICE_LIST DCMD, this patch refactors the code in the AEN event handling path. Add new function to update the PD and LD list in driver. Move the code to scan PD and VD channels into separate function. Signed-off-by:
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Shivasharan S authored
During FW init, combine the code to get the PD and LD list from FW into a single function. This patch is in preparation for adding support for HOST_DEVICE_LIST DCMD. Signed-off-by:
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