- 12 Jul, 2011 40 commits
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Scott Wood authored
Previously, these macros hardcoded THREAD_EVR0 as the base of the save area, relative to the base register passed. This base offset is now passed as a separate macro parameter, allowing reuse with other SPE save areas, such as used by KVM. Acked-by:
Kumar Gala <galak@kernel.crashing.org> Signed-off-by:
Scott Wood <scottwood@freescale.com> Signed-off-by:
Alexander Graf <agraf@suse.de>
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yu liu authored
giveup_spe() saves the SPE state which is protected by MSR[SPE]. However, modifying SPEFSCR does not trap when MSR[SPE]=0. And since SPEFSCR is already saved/restored in _switch(), not all the callers want to save SPEFSCR again. Thus, saving SPEFSCR should not belong to giveup_spe(). This patch moves SPEFSCR saving to flush_spe_to_thread(), and cleans up the caller that needs to save SPEFSCR accordingly. Signed-off-by:
Liu Yu <yu.liu@freescale.com> Acked-by:
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Alexander Graf authored
Up until now, Book3S KVM had variables stored in the kernel that a kernel module or the kvm code in the kernel could read from to figure out where some real mode helper functions are located. This is all unnecessary. The high bits of the EA get ignore in real mode, so we can just use the pointer as is. Also, it's a lot easier on relocations when we use the normal way of resolving the address to a function, instead of jumping through hoops. This patch fixes compilation with CONFIG_RELOCATABLE=y. Signed-off-by: -
Stuart Yoder authored
When http://www.spinics.net/lists/kvm-ppc/msg02664.html was applied to produce commit b51e7aa7ed6d8d134d02df78300ab0f91cfff4d2, the removal of the conversion in add_exit_timing was left out. Signed-off-by:
Stuart Yoder <stuart.yoder@freescale.com> Signed-off-by:
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Avi Kivity authored
kvm_set_cr0() and kvm_set_cr4(), and possible other functions, assume that kvm_mmu_reset_context() flushes the guest TLB. However, it does not. Fix by flushing the tlb (and syncing the new root as well). Signed-off-by:Avi Kivity <avi@redhat.com>
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Avi Kivity authored
When CR0.WP=0, we sometimes map user pages as kernel pages (to allow the kernel to write to them). Unfortunately this also allows the kernel to fetch from these pages, even if CR4.SMEP is set. Adjust for this by also setting NX on the spte in these circumstances. Signed-off-by: -
Yang, Wei authored
This patch exposes ERMS feature to KVM guests. The REP MOVSB/STOSB instruction can enhance fast strings attempts to move as much of the data with larger size load/stores as possible. Signed-off-by:
Yang, Wei <wei.y.yang@intel.com> Signed-off-by:
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Yang, Wei authored
This patch exposes RDWRGSFS bit to KVM guests. Signed-off-by:
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Yang, Wei authored
This patch adds RDWRGSFS support when setting CR4. Signed-off-by:
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Yang, Wei authored
This patch removes RDWRGSFS bit from CR4_RESERVED_BITS. Signed-off-by:
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Yang, Wei Y authored
This patch exposes DRNG feature to KVM guests. The RDRAND instruction can provide software with sequences of random numbers generated from white noise. Signed-off-by:
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Andre Przywara authored
commit 123108f1c1aafd51d6a5c79cc04d7999dd88a930 tried to fix KVMs XSAVE valid feature scanning, but it was wrong. It was not considering the sparse nature of this bitfield, instead reading values from uninitialized members of the entries array. This patch now separates subleaf indicies from KVM's array indicies and fills the entry before querying it's value. This fixes AVX support in KVM guests. Signed-off-by:
Andre Przywara <andre.przywara@amd.com> Signed-off-by:
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Jan Kiszka authored
The documented behavior did not match the implemented one (which also never changed). Signed-off-by:
Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by:
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Jan Kiszka authored
KVM_MAX_MSIX_PER_DEV implies that up to that many MSI-X entries can be requested. But the kernel so far rejected already the upper limit. Signed-off-by:
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Alexander Graf authored
KVM has an ioctl to define which signal mask should be used while running inside VCPU_RUN. At least for big endian systems, this mask is different on 32-bit and 64-bit systems (though the size is identical). Add a compat wrapper that converts the mask to whatever the kernel accepts, allowing 32-bit kvm user space to set signal masks. This patch fixes qemu with --enable-io-thread on ppc64 hosts when running 32-bit user land. Signed-off-by:
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Jan Kiszka authored
Neither host_irq nor the guest_msi struct are used anymore today. Tag the former, drop the latter to avoid confusion. Signed-off-by:
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Yang, Wei Y authored
This patch adds instruction fetch checking when walking guest page table, to implement SMEP when emulating instead of executing natively. Signed-off-by:
Shan, Haitao <haitao.shan@intel.com> Signed-off-by:
Li, Xin <xin.li@intel.com> Signed-off-by:
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Yang, Wei Y authored
This patch masks CPUID leaf 7 ebx against host capability word9. Signed-off-by:
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Yang, Wei Y authored
This patch adds SMEP handling when setting CR4. Signed-off-by:
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Yang, Wei Y authored
This patch removes SMEP bit from CR4_RESERVED_BITS. Signed-off-by:
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Nadav Har'El authored
The nested VMX feature is supposed to fully emulate VMX for the guest. This (theoretically) not only allows it to run its own guests, but also also to further emulate VMX for its own guests, and allow arbitrarily deep nesting. This patch fixes a bug (discovered by Kevin Tian) in handling a VMLAUNCH by L2, which prevented deeper nesting. Deeper nesting now works (I only actually tested L3), but is currently *absurdly* slow, to the point of being unusable. Signed-off-by:
Nadav Har'El <nyh@il.ibm.com> Signed-off-by:
Marcelo Tosatti <mtosatti@redhat.com>
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Jan Kiszka authored
Signed-off-by:
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Avi Kivity authored
This saves a lot of pointless casts x86_emulate_ctxt and decode_cache. Signed-off-by:
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Avi Kivity authored
The name eip conflicts with a field of the same name in x86_emulate_ctxt, which we plan to fold decode_cache into. The name _eip is unfortunate, but what's really needed is a refactoring here, not a better name. Signed-off-by:
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Jan Kiszka authored
a is unused now on CONFIG_X86_32. Signed-off-by:
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Takuya Yoshikawa authored
Signed-off-by:
Takuya Yoshikawa <yoshikawa.takuya@oss.ntt.co.jp> Signed-off-by:
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Takuya Yoshikawa authored
LOOP/LOOPcc : E0-E2 JCXZ/JECXZ/JRCXZ : E3 Signed-off-by:
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Takuya Yoshikawa authored
Call emulate_int() directly to avoid spaghetti goto's. Signed-off-by:
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Takuya Yoshikawa authored
Different functions for those which take segment register operands. Signed-off-by:
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Takuya Yoshikawa authored
Signed-off-by:
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Takuya Yoshikawa authored
In addition, replace one "goto xchg" with an em_xchg() call. Signed-off-by:
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Takuya Yoshikawa authored
Signed-off-by:
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Takuya Yoshikawa authored
Move the following functions to the opcode tables: RET (Far return) : CB IRET : CF JMP (Jump far) : EA SYSCALL : 0F 05 CLTS : 0F 06 SYSENTER : 0F 34 SYSEXIT : 0F 35 Signed-off-by:
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Takuya Yoshikawa authored
The next patch will change these to be called by opcode::execute. Signed-off-by:
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Takuya Yoshikawa authored
We should use the local variables ctxt and c when the emulate_ctxt and decode appears many times. At least, we need to be consistent about how we use these in a function. Signed-off-by:
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Sasha Levin authored
Document KVM_IOEVENTFD that can be used to receive notifications of PIO/MMIO events without triggering an exit. Signed-off-by:
Sasha Levin <levinsasha928@gmail.com> Signed-off-by:
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Nadav Har'El authored
This patch includes a brief introduction to the nested vmx feature in the Documentation/kvm directory. The document also includes a copy of the vmcs12 structure, as requested by Avi Kivity. [marcelo: move to Documentation/virtual/kvm] Signed-off-by:
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Nadav Har'El authored
Small corrections of KVM (spelling, etc.) not directly related to nested VMX. Signed-off-by:
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Nadav Har'El authored
If the "nested" module option is enabled, add the "VMX" CPU feature to the list of CPU features KVM advertises with the KVM_GET_SUPPORTED_CPUID ioctl. Qemu uses this ioctl, and intersects KVM's list with its own list of desired cpu features (depending on the -cpu option given to qemu) to determine the final list of features presented to the guest. Signed-off-by:
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Nadav Har'El authored
In the unlikely case that L1 does not capture MSR_IA32_TSC, L0 needs to emulate this MSR write by L2 by modifying vmcs02.tsc_offset. We also need to set vmcs12.tsc_offset, for this change to survive the next nested entry (see prepare_vmcs02()). Additionally, we also need to modify vmx_adjust_tsc_offset: The semantics of this function is that the TSC of all guests on this vcpu, L1 and possibly several L2s, need to be adjusted. To do this, we need to adjust vmcs01's tsc_offset (this offset will also apply to each L2s we enter). We can't set vmcs01 now, so we have to remember this adjustment and apply it when we later exit to L1. Signed-off-by:
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