- 26 Sep, 2017 40 commits
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Charlene Liu authored
Signed-off-by:
Charlene Liu <charlene.liu@amd.com> Reviewed-by:
Yongqiang Sun <yongqiang.sun@amd.com> Acked-by:
Harry Wentland <Harry.Wentland@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Eric Yang authored
On boot, hubp 0 is powergated during enable accel mode, so we time out when we try to blank in undo wa. Fix: Check power gate status before set blank Signed-off-by:
Eric Yang <Eric.Yang2@amd.com> Reviewed-by:
Hersen Wu <hersenxs.wu@amd.com> Acked-by:
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Andrey Grodzovsky authored
dis_clk is single instance across pipes. Signed-off-by:
Andrey Grodzovsky <Andrey.Grodzovsky@amd.com> Reviewed-by:
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Charlene Liu authored
Signed-off-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
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Mikita Lipski authored
Fix to allow DVI displays to share the same clock source Signed-off-by:
Mikita Lipski <mikita.lipski@amd.com> Reviewed-by:
Roman Li <Roman.Li@amd.com> Acked-by:
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Bhawanpreet Lakha authored
Rename dc_resource methods from validate_ctx to state Signed-off-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by:
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Jerry Zuo authored
Rename all the dc validate_context to dc_state and dc current_context to current_state. Signed-off-by:
Jerry Zuo <Jerry.Zuo@amd.com> Reviewed-by:
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Yue Hin Lau authored
Signed-off-by:
Yue Hin Lau <Yuehin.Lau@amd.com> Reviewed-by:
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Yongqiang Sun authored
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Hersen Wu authored
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Yue Hin Lau authored
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Eric Bernstein authored
Signed-off-by:
Eric Bernstein <eric.bernstein@amd.com> Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
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Jerry Zuo authored
The fix is for the scenario: MST+SST chain together, and hook up to the card. Regression: Per stream validate_context build v2 Before dc_add_stream_to_ctx(), need to update/reset stream signal type to SIGNAL_TYPE_DISPLAY_PORT_MST. Otherwise, downstream device cannot be added to ctx due to the lack of signal type info (SIGNAL_TYPE_NONE). update_stream_signal() needs to be done after stream is created. Signed-off-by:
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Andrey Grodzovsky authored
Starting with 4.12 kernel DRM provides page flip flags so we don't need to have our own copy. Signed-off-by:
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Yongqiang Sun authored
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Wenjing Liu authored
[Description] According to DP1.4 specs we should not reset lane count back when falling back in failing EQ training. This causes PHY test pattern compliance to fail as infinite LT when LT fails EQ to 4 RBR and fails CR in a loop. Signed-off-by:
Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by:
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Bhawanpreet Lakha authored
Clean up some code related to flattening core_dc commit (Remove redundent dc = dc, which was the result of removing DC_TO_CORE() macro) Signed-off-by:
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Darren Salt authored
Noticed while playing “Valley”, which was causing some 8MB of leakage per second. kmemleak listed many entries looking like this: unreferenced object 0xffff8802c2951800 (size 1024): comm "Xorg", pid 2982, jiffies 4297410155 (age 392.787s) hex dump (first 32 bytes): 00 50 f9 0c 04 88 ff ff 98 08 00 00 00 00 00 00 .P.............. 80 07 00 00 00 00 00 00 58 00 00 00 2c 00 00 00 ........X...,... backtrace: [<ffffffff810cd4c3>] create_object+0x13c/0x261 [<ffffffff815abdc2>] kmemleak_alloc+0x20/0x3c [<ffffffff810cad1d>] slab_post_alloc_hook+0x42/0x52 [<ffffffff810cb8e0>] kmem_cache_alloc+0x67/0x76 [<ffffffff813bbb54>] dc_create_stream_for_sink+0x24/0x1cf [<ffffffff81373aaa>] create_stream_for_sink+0x6f/0x295 [<ffffffff81373dc2>] dm_update_crtcs_state+0xa6/0x268 [<ffffffff8137401e>] amdgpu_dm_atomic_check+0x9a/0x314 [<ffffffff812ac3dd>] drm_atomic_check_only+0x17a/0x42d [<ffffffff812ac6a3>] drm_atomic_commit+0x13/0x4b [<ffffffff812ad1a5>] drm_atomic_connector_commit_dpms+0xcb/0xe8 [<ffffffff812b1238>] drm_mode_obj_set_property_ioctl+0xe6/0x1e3 [<ffffffff812b027b>] drm_mode_connector_property_set_ioctl+0x2b/0x2d [<ffffffff8129f427>] drm_ioctl_kernel+0x64/0x9d [<ffffffff8129f6a2>] drm_ioctl+0x230/0x316 [<ffffffff812ca4d3>] amdgpu_drm_ioctl+0x4b/0x7d v2: also handle break statements. Signed-off-by:Darren Salt <devspam@moreofthesa.me.uk> Reviewed-by:
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Andrey Grodzovsky authored
Split into update crtcs and update plane functions. Signed-off-by:
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Andrey Grodzovsky authored
Introduce add/remove plane to/from context. Make DC wrapper to use them in WIndows/Diags. Use them in dc_update_surface_to_stream. Call add/remove plane from Linux DM. Remove dc_validation_set from dc_validate_global_state interface and by this remove clean Linux DM from using it. Signed-off-by:
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Charlene Liu authored
Signed-off-by:
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Wenjing Liu authored
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Wenjing Liu authored
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Harry Wentland authored
It's already included in atomfirmware.h Signed-off-by:
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Harry Wentland authored
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Bhawanpreet Lakha authored
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Wenjing Liu authored
[Description] Link training is not retried in automated link training request. In case link training is occasionally failing, there is not way to retry so the requested lane settings will not set. Signed-off-by:
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Bhawanpreet Lakha authored
Change log level from LOG_DC to LOG_DEBUG LOG_DC spams dmesg on linux when hotpluging Signed-off-by:
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Tony Cheng authored
set dcfclk and fclk req with pp_smu_display_requirement_rv Signed-off-by:
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Charlene Liu authored
Signed-off-by:
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Tony Cheng authored
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Yongqiang Sun authored
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Harry Wentland authored
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Tony Cheng authored
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Yue Hin Lau authored
Signed-off-by:
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Dmytro Laktyushkin authored
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Dmytro Laktyushkin authored
This should be handled by mi and mpc only Signed-off-by:
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Harry Wentland authored
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Bhawanpreet Lakha authored
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Jerry Zuo authored
1. Change 100104: Move verify link cap after read edid causes MST link_cap struct not being set. It leads to zero denominator pbn_per_slot value, leading to the crash at dal_fixed31_32_div(). Skip MST link training for now and will need to add MST specific link traning routine later. 2. Change 98822: Adding edp supports changes link setting condition from max_link to verified_link. It leads to MST is getting wrong link settings. e.g. LINK_SPREAD_05_DOWNSPREAD_30KHZ not set in MST case Signed-off-by:
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