1. 22 Oct, 2019 1 commit
  2. 18 Oct, 2019 12 commits
  3. 15 Oct, 2019 21 commits
  4. 09 Oct, 2019 2 commits
  5. 08 Oct, 2019 3 commits
    • Mark Brown's avatar
    • Frieder Schrempf's avatar
      spi: spi-fsl-qspi: Clear TDH bits in FLSHCR register · f6910679
      Frieder Schrempf authored
      Later versions of the QSPI controller (e.g. in i.MX6UL/ULL and i.MX7)
      seem to have an additional TDH setting in the FLSHCR register, that
      needs to be set in accordance with the access mode that is used (DDR
      or SDR).
      
      Previous bootstages such as BootROM or bootloader might have used the
      DDR mode to access the flash. As we currently only use SDR mode, we
      need to make sure the TDH bits are cleared upon initialization.
      
      Fixes: 84d04318 ("spi: Add a driver for the Freescale/NXP QuadSPI controller")
      Cc: <stable@vger.kernel.org>
      Signed-off-by: default avatarFrieder Schrempf <frieder.schrempf@kontron.de>
      Acked-by: default avatarHan Xu <han.xu@nxp.com>
      Link: https://lore.kernel.org/r/20191007071933.26786-1-frieder.schrempf@kontron.deSigned-off-by: default avatarMark Brown <broonie@kernel.org>
      f6910679
    • Vladimir Oltean's avatar
      spi: spi-fsl-dspi: Always use the TCFQ devices in poll mode · 5d2af8bc
      Vladimir Oltean authored
      With this patch, the "interrupts" property from the device tree bindings
      is ignored, even if present, if the driver runs in TCFQ mode.
      
      Switching to using the DSPI in poll mode has several distinct
      benefits:
      
      - With interrupts, the DSPI driver in TCFQ mode raises an IRQ after each
        transmitted word. There is more time wasted for the "waitq" event than
        for actual I/O. And the DSPI IRQ count can easily get the largest in
        /proc/interrupts on Freescale boards with attached SPI devices.
      
      - The SPI I/O time is both lower, and more consistently so. Attached to
        some Freescale devices are either PTP switches, or SPI RTCs. For
        reading time off of a SPI slave device, it is important that all SPI
        transfers take a deterministic time to complete.
      
      - In poll mode there is much less time spent by the CPU in hardirq
        context, which helps with the response latency of the system, and at
        the same time there is more control over when interrupts must be
        disabled (to get a precise timestamp measurement): win-win.
      
      On the LS1021A-TSN board, where the SPI device is a SJA1105 PTP switch
      (with a bits_per_word=8 driver), I created a "benchmark" where I read
      its PTP time once per second, for 120 seconds. Each "read PTP time" is a
      12-byte SPI transfer. I then recorded the time before putting the first
      byte in the TX FIFO, and the time after reading the last byte from the
      RX FIFO. That is the transfer delay in nanoseconds.
      
      Interrupt mode:
      
        delay: min 125120 max 168320 mean 150286 std dev 17675.3
      
      Poll mode:
      
        delay: min 69440 max 119040 mean 70312.9 std dev 8065.34
      
      Both the mean latency and the standard deviation are more than 50% lower
      in poll mode than in interrupt mode. This is with an 'ondemand' governor
      on an otherwise idle system - therefore running mostly at 600 MHz out of
      a max of 1200 MHz.
      Signed-off-by: default avatarVladimir Oltean <olteanv@gmail.com>
      Link: https://lore.kernel.org/r/20190905010114.26718-5-olteanv@gmail.comSigned-off-by: default avatarMark Brown <broonie@kernel.org>
      5d2af8bc
  6. 07 Oct, 2019 1 commit
    • Vladimir Oltean's avatar
      spi: spi-fsl-dspi: Implement the PTP system timestamping for TCFQ mode · d6b71dfa
      Vladimir Oltean authored
      In this mode, the DSPI controller uses PIO to transfer word by word. In
      comparison, in EOQ mode the 4-word deep FIFO is being used, hence the
      current logic will need some adaptation for which I do not have the
      hardware (Coldfire) to test. It is not clear what is the timing of DMA
      transfers and whether timestamping in the driver brings any overall
      performance increase compared to regular timestamping done in the core.
      
      Short phc2sys summary after 58 minutes of running on LS1021A-TSN with
      interrupts disabled during the critical section:
      
        offset: min -26251 max 16416 mean -21.8672 std dev 863.416
        delay: min 4720 max 57280 mean 5182.49 std dev 1607.19
        lost servo lock 3 times
      
      Summary of the same phc2sys service running for 120 minutes with
      interrupts disabled:
      
        offset: min -378 max 381 mean -0.0083089 std dev 101.495
        delay: min 4720 max 5920 mean 5129.38 std dev 154.899
        lost servo lock 0 times
      
      The minimum delay (pre to post time) in nanoseconds is the same, but the
      maximum delay is quite a bit higher, due to interrupts getting sometimes
      executed and interfering with the measurement. Hence set disable_irqs
      whenever possible (aka when the driver runs in poll mode - otherwise it
      would be a contradiction in terms).
      Signed-off-by: default avatarVladimir Oltean <olteanv@gmail.com>
      Link: https://lore.kernel.org/r/20190905010114.26718-4-olteanv@gmail.comSigned-off-by: default avatarMark Brown <broonie@kernel.org>
      d6b71dfa