- 06 Dec, 2012 40 commits
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Al Cooper authored
If "caps2" host capabilities does not indicate support for MMC HS200, don't allow clock speeds >52MHz. Currently, for MMC, the clock speed is set to the lesser of the max speed the eMMC module supports (card->ext_csd.hs_max_dtr) or the max base clock of the host controller (host->f_max based on BASE_CLK_FREQ in the host CAPS register). This means that a host controller that doesn't support HS200 mode but has a base clock of 100MHz and an eMMC module that supports HS200 speeds will end up using a 100MHz clock. Signed-off-by:
Al Cooper <alcooperx@gmail.com> Signed-off-by:
Chris Ball <cjb@laptop.org>
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Seungwon Jeon authored
Use managed device resource functions for easy handling. This makes driver simpler in the routine of error and exit. Signed-off-by:
Seungwon Jeon <tgih.jun@samsung.com> Acked-by:
James Hogan <james.hogan@imgtec.com> Signed-off-by:
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Guennadi Liakhovetski authored
MMCIF only uses one clock, all ARM and SuperH platforms register MMCIF clock lookup entries with no connection ID, hence it can be dropped in the driver too. Signed-off-by:
Guennadi Liakhovetski <g.liakhovetski@gmx.de> Reviewed-by:
Simon Horman <horms+renesas@verge.net.au> Signed-off-by:
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Guennadi Liakhovetski authored
SDHI only uses one clock, all ARM and SuperH platform register SDHI clock lookup entries with no connection ID, hence it can be dropped in the driver too. Signed-off-by:
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Guennadi Liakhovetski authored
During its probing the SDHI driver prints out the clock frequency, but does it wrongly, always reporting 0Hz. Use the MMC host frequency value to fix this issue. Signed-off-by:
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Sachin Kamat authored
kfree on a null pointer is a no-op. Signed-off-by:
Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by:
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Sachin Kamat authored
kfree on a null pointer is a no-op. Signed-off-by:
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Shawn Guo authored
Use devm_kzalloc, devm_gpio_request_one and devm_request_irq to make cleanup path simpler. Signed-off-by:
Shawn Guo <shawn.guo@linaro.org> Signed-off-by:
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Daniel Drake authored
The OLPC XO-1.75 laptop includes a SDHCI controller which is 1.8v capable, and it truthfully reports so in its capabilities. This alternate voltage is used for driving new "UHS-I" SD cards at their full speed. However, what the controller doesn't know is that the motherboard physically doesn't have a 1.8v supply available, so attempting to switch to the 1.8v level will result in a situation that cannot be recovered from without physically replugging the SD card. Add a device tree flag that can be used on systems like these, and hook it up to the equivalent SDHCI quirk. Signed-off-by:
Daniel Drake <dsd@laptop.org> Reviewed-by:
Philip Rakity <prakity@nvidia.com> Signed-off-by:
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Daniel Drake authored
The OLPC XO-1.75 laptop includes a SDHCI controller which is 1.8v capable, and it truthfully reports so in its capabilities. This alternate voltage is used for driving new "UHS-I" SD cards at their full speed. However, what the controller doesn't know is that the motherboard physically doesn't have a 1.8v supply available. Add a quirk so that systems such as this one can override disable 1.8v support, adding support for UHS-I cards (by running them at 3.3v). This avoids a problem where the system would first try to run the card at 1.8v, fail, and then not be able to fully reset the card to retry at the normal 3.3v voltage. This is more appropriate than using the MISSING_CAPS quirk, which is intended for cases where the SDHCI controller is actually lying about its capabilities, and would force us to somehow override both caps words from another source. Signed-off-by:
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Rafael J. Wysocki authored
Suspend methods provided by SDIO drivers are not supposed to be called by the PM core. Instead, when the SDIO core gets to suspend a device's ancestor, it calls the device driver's suspend routine. However, the PM core executes suspend callback routines directly for device drivers whose bus types don't provide suspend callbacks. In consequece, because the SDIO bus type doesn't provide a suspend callback, the SDIO drivers' suspend routines will be executed by the PM core (which shouldn't happen). To prevent this from happening, add empty system suspend/resume callbacks for the SDIO bus type. An analogous change had been made already by commit (e841a7c6 mmc: sdio: Use empty system suspend/resume callbacks at the bus level), but then it was reverted inadvertently by commit (d8e2ac33 mmc: sdio: Fix PM_SLEEP related build warnings) that attempted to fix build warnings introduced by commit e841a7c6. Reported-by:
NeilBrown <neilb@suse.de> Signed-off-by:
Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by:
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Marina Makienko authored
Add missing usb_put_dev on failure path in vub300_probe(). Found by Linux Driver Verification project (linuxtesting.org). Signed-off-by:
Marina Makienko <makienko@ispras.ru> Signed-off-by:
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Viresh Kumar authored
clk_{un}prepare is mandatory for platforms using common clock framework. Because for SPEAr we don't do anything in clk_{un}prepare() calls, just call them once in probe/remove. Signed-off-by:Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by:
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Vipul Kumar Samar authored
SPEAr sdhci driver expects the clock to be set to 50 MHz for proper functioning. This patch sets clk to 50 MHz in probe. Signed-off-by:
Vipul Kumar Samar <vipulkumar.samar@st.com> Signed-off-by:
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Tomasz Figa authored
This patch adds support for pin configuration using pinctrl subsystem to the sdhci-s3c driver. Signed-off-by:
Tomasz Figa <t.figa@samsung.com> Acked-by:
Thomas Abraham <thomas.abraham@linaro.org> Signed-off-by:
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Tomasz Figa authored
The set of GPIO pins used by sdhci-s3c driver varies between configurations, such as card detect method, pinctrl availability, etc. This overly complicates the code requesting and freeing GPIO pins, which must check which pins are used, when freeing them. This patch modifies the sdhci-s3c driver to use devm_gpio_request to free requested pins automatically after unbinding the driver. Signed-off-by:
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Jerry Huang authored
The IP versions older than 2.3 didn't support commands with busy response which expect the TC bit set. But after the VVN2.3, eSDHC IP has supported it. Signed-off-by:
Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by:
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Tushar Behera authored
The third argument for of_get_property() is a pointer, hence pass NULL instead of 0. Fixes the following sparse warning: sdhci-s3c.c:452:48: warning: Using plain integer as NULL pointer sdhci-s3c.c:457:52: warning: Using plain integer as NULL pointer Signed-off-by:
Tushar Behera <tushar.behera@linaro.org> Signed-off-by:
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Venkatraman S authored
Define the most frequently used bitmasks of the Interrupt Enable / Interrupt Status register with consistent naming ( with _EN suffix). Use meaningful concatenation of bitfields for INT_EN_MASK, which shows which interrupts are enabled by default. No functional changes. Signed-off-by:
Venkatraman S <svenkatr@ti.com> Acked-by:
Felipe Balbi <balbi@ti.com> Signed-off-by:
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Venkatraman S authored
Fatal errors for the driver are not reported when just error debug is enabled. Convert selected dev_dbg to dev_err for accurate error reporting. Reported-by:
Benoit Cousson <b-cousson@ti.com> Signed-off-by:
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Felipe Balbi authored
prepare() is supposed to prevent new children from being registered. On the MMC subsystem, children (new cards) registration starts with the card detect IRQ. Move card detect IRQ disabling to prepare() so that no new cards will be registered while we're trying to suspend. Likewise, move card detect IRQ enabling to complete() so we only try to register new children after our MMC IP is back up. Signed-off-by:
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Hebbar, Gururaja authored
HSMMC IP on AM33xx need a special setting to handle High-speed cards. Other platforms like TI81xx, OMAP4 may need this as-well. This depends on the HSMMC IP timing closure done for the high speed cards. From AM335x TRM (SPRUH73F - 18.3.12 Output Signals Generation): The MMC/SD/SDIO output signals can be driven on either falling edge or rising edge depending on the SD_HCTL[2] HSPE bit. This feature allows to reach better timing performance, and thus to increase data transfer frequency. There are few pre-requisites for enabling the HSPE bit - Controller should support High-Speed-Enable Bit and - Controller should not be using DDR Mode and - Controller should advertise that it supports High Speed in capabilities register and - MMC/SD clock coming out of controller > 25MHz Signed-off-by:
Hebbar, Gururaja <gururaja.hebbar@ti.com> Signed-off-by:
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Balaji T K authored
Update error code to cmd->error for commands with response_busy and no data. Signed-off-by:
Balaji T K <balajitk@ti.com> Reviewed-by:
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Balaji T K authored
Avoid soft reset of command internal state machine on data errors. Signed-off-by:
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Balaji T K authored
ae4bf788 ("mmc: omap_hsmmc: consolidate error report handling of HSMMC IRQ") sets both end_cmd and end_trans to 1. Setting end_cmd to 1 for Data Timeout/CRC leads to NULL pointer dereference of host->cmd as the command complete has previously been handled. Set end_cmd only in case of command Timeout/CRC. Moreover host->cmd->error should not be updated on data error case, only host->data->error needs to be updated. Signed-off-by:
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Abhilash Kesavan authored
Add dt-based retrieval of host sdio pm capabilities. Based on the dt based discovery do a bus init in the resume function. Signed-off-by:
Olof Johansson <olofj@chromium.org> Signed-off-by:
Abhilash Kesavan <a.kesavan@samsung.com> Signed-off-by:
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Abhilash Kesavan authored
Add support for optional pm capabilities such as MMC_PM_KEEP_POWER and MMC_PM_WAKE_SDIO_IRQ. Signed-off-by:
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Abhilash Kesavan authored
Add documentation for pm capabilties such as MMC_PM_KEEP_POWER and MMC_PM_WAKE_SDIO_IRQ. Signed-off-by:
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Abhilash Kesavan authored
Fix typo in the synopsis dwmmc controller dt binding filename. Signed-off-by:
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Kevin Liu authored
Acked-by:
Zhangfei Gao <zhangfei.gao@marvell.com> Signed-off-by:
Kevin Liu <kliu5@marvell.com> Signed-off-by:
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Kevin Liu authored
For regulator vmmc/vmmcq, use voltage range as below 3.3v/3.0v: (2.7v, 3.6v) 1.8v: (1.7v, 1.95v) Original code uses the precise value which may fail in regulator driver if it does NOT support the precise voltage. Signed-off-by:
Jialing Fu <jlfu@marvell.com> Signed-off-by:
Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by:
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Tony Prisk authored
This patch adds support for the SD/MMC host controller found on Wondermedia 8xxx series SoCs, currently supported under arm/arch-vt8500. A binding document is also included, based on mmc.txt with additional properties. Signed-off-by:
Tony Prisk <linux@prisktech.co.nz> Signed-off-by:
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Loic Pallardy authored
RPMB partition is accessing though /dev/block/mmcXrpmb device User callers can read and write entire data frame(s) as defined by JEDEC Standard JESD84-A441, using standard IOCTL interface. Signed-off-by:
Alex Macro <alex.macro@stericsson.com> Signed-off-by:
Loic Pallardy <loic.pallardy@stericsson.com> Reviewed-by:
Namjae Jeon <linkinjeon@gmail.com> Acked-by:
Linus Walleij <linus.walleij@linaro.org> Acked-by:
Krishna Konda <kkonda@codeaurora.org> Signed-off-by:
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Loic Pallardy authored
Provide support for automatically sending Set Block Count (CMD23) messages. Used at least for RPMB support. Signed-off-by:
Johan Rudholm <johan.rudholm@stericsson.com> Acked-by:
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Loic Pallardy authored
Extend current sysfs access to ext_csd rpmb parameters (RPMB partition size) and rel_sector information. Signed-off-by:
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Loic Pallardy authored
Do not scan rpmb partitions for "soft" partitions, since the rpmb partition contains protected data. Silences the following message during boot: mmcblkXRPMB: unknown partition table Signed-off-by:
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Loic Pallardy authored
Following JEDEC standard, if the mmc supports RPMB partition, a new interface is created and exposed via /dev/block. Users will be able to access RPMB partition using standard mmc IOCTL commands. Signed-off-by:
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Kevin Liu authored
Both of MMC_TIMING_LEGACY and MMC_TIMING_UHS_SDR12 are defined to 0. And ios->timing is set to MMC_TIMING_LEGACY during power up. But set_ios can't distinguish these two timing if host support spec 3.0. Just adjust timing values to be different can resolve this issue without any other impact. Reviewed-by:
Girish K S <girish.shivananjappa@linaro.org> Acked-by:
Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by:
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Kevin Liu authored
Enable the quirk SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN since SD_CAPABILITIES_1[15:8](BASE_FREQ) can't get correct base clock value. It returns a fixed pre-set value like 200 on some sdhci-pxav3 based platforms like MMP3 while return 0 on the other sdhci-pxav3 based platforms. So we enable the quirk and get the base clock via function get_max_clock. Also add get_max_clock. Reported-by:
Philip Rakity <prakity@marvell.com> Reviewed-by:
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Lee Jones authored
There are discrepancies with regards to how MMC capabilities are carried throughout the subsystem. Let's standardise them to eliminate any confusion. Signed-off-by:
Lee Jones <lee.jones@linaro.org> Signed-off-by:
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