- 23 Oct, 2018 9 commits
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Lionel Landwerlin authored
The way our hardware is designed doesn't seem to let us use the MI_RECORD_PERF_COUNT command without setting up a circular buffer. In the case where the user didn't request OA reports to be available through the i915 perf stream, we can set the OA buffer to the minimum size to avoid consuming memory which won't be used by the driver. v2: Simplify oa buffer size exponent selection (Chris) Reuse vma size field (Lionel) v3: Restrict size opening parameter to values supported by HW (Chris) v4: Drop out of date comment (Matt) Add debug message when buffer size is rejected (Matt) Signed-off-by:Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by:
Matthew Auld <matthew.auld@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181023100707.31738-5-lionel.g.landwerlin@intel.com
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Lionel Landwerlin authored
We want to use some of the properties of the perf stream to program the hardware in a later commit. v2: Pass only perf stream as argument (Matthew) Signed-off-by:
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Lionel Landwerlin authored
We initialize the OA buffer everytime we enable the OA unit (first call in gen[78]_oa_enable), so we don't need to initialize when preparing the metric set. Signed-off-by:
Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181023100707.31738-3-lionel.g.landwerlin@intel.com
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Lionel Landwerlin authored
Lucas submitted a patch to generator script, so just reflecting the change here. Signed-off-by:
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Daniele Ceraolo Spurio authored
commit e346a991 ("drm/i915/guc: drop negative doorbell alloc selftest") removed the negative case from the selftest and left no code between the goto from the positive case of the test and the label itself, so we can get rid of it. Reported-by:
Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Reviewed-by:
Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20181022230427.5616-5-daniele.ceraolospurio@intel.com
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Daniele Ceraolo Spurio authored
We stopped supporting fallback to execlists in commit 121981fa (drm/i915/guc: Combine enable_guc_loading|submission modparams). We do instead reset and retry in some cases, depending on the workarounds required by the platform. Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
Michal Wajdeczko <michal.wajdeczko@intel.com> Signed-off-by:
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Daniele Ceraolo Spurio authored
A collection of very small cleanups/improvements around doorbell checking that do not deserve their own patch: - Move doorbell-related HW defs to intel_guc_reg.h - use GUC_NUM_DOORBELLS instead of GUC_DOORBELL_INVALID where appropriate - do not stop on error in guc_verify_doorbells - do not print drbreg on error: the only content of the register apart from the valid bit is the lower part of the physical memory address, which we can't use even if valid because we don't know which descriptor it came from (since the doorbell is in an unexpected state) - Move the checking of doorbell valid bit to a common helper. v2: add more cleanups (move defs, use GUC_NUM_DOORBELLS, don't stop in guc_verify_doorbells) (Michal) v3: move more things to intel_guc_reg, redefine GUC_DOORBELL_INVALID (Michal), drop guc_doorbell_qw since it just duplicates guc_doorbell_info Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Signed-off-by: -
Daniele Ceraolo Spurio authored
Cacheline selection is only needed if we actually manage to reserve a doorbell. Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Reviewed-by:
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Daniele Ceraolo Spurio authored
The 2 functions don't create or destroy anything, they just update the doorbell state in memory. Use init and fini instead for clarity. Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Reviewed-by:
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- 22 Oct, 2018 21 commits
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Rodrigo Vivi authored
No functional change. Just sorting this "if" statement from newer to older platform. Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181022171526.15641-5-rodrigo.vivi@intel.com
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Rodrigo Vivi authored
No functional change. Just sorting this "if" block from newer to older platform. v2: Fix few positions (Ville) Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by:
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Rodrigo Vivi authored
Just sorting this "if" block from newer to older platform. The main difference here is the addition of a missing case with return false that should never occur. And if it occurs it is better than to raise a warn than use the icl one. The gen >= 11 was already present in the previous logic, although hidden. So, in summary no real functional change. Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by:
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Rodrigo Vivi authored
No functional change. Just sorting this "if" block from newer to older platform. Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by:
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Rodrigo Vivi authored
No functional change. Just sorting this "if" block from newer to older platform. v2: Invert gen9_bc and gen9_lp (Ville) Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by:
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Madhav Chauhan authored
This patch defines DSI_CMD_RXCTL, DSI_CMD_TXCTL registers, bitfields, masks and macros used for configuring DSI panel. v2: Define remaining bitfields v3 by Jani: - Alignment fix Signed-off-by:
Madhav Chauhan <madhav.chauhan@intel.com> Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/37b41fe08ce50c3d9ef7d55c03d12a8a10a252d6.1539613303.git.jani.nikula@intel.com
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Madhav Chauhan authored
This patch enables DSI transcoders by writing to TRANS_CONF registers and wait for its state to be enabled. v2 by Jani: - Rebase Signed-off-by:
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Madhav Chauhan authored
This patch defines TRANS_CONF registers for DSI ports 0 and 1. Bitfields of these registers used for enabling and reading the current state of transcoder. v2: Add blank line before comment v3 by Jani: - Move DSI specific .pipe_offsets to GEN11_FEATURES - Macro placement and comment juggling Signed-off-by:
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Madhav Chauhan authored
As part of DSI enable sequence, transcoder timings (horizontal & vertical) need to be set so that transcoder will generate the stream output as per those timings. This patch set required transcoder timings as per BSPEC. v2: Remove TRANS_TIMING_SHIFT usage v3 by Jani: - Rebase - Reduce temp variable use - Checkpatch fix Signed-off-by:
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Madhav Chauhan authored
This patch defines registers and bitfields used for programming DSI transcoder's horizontal and vertical timings. v2: Remove TRANS_TIMING_SHIFT definition v3 by Jani: - Group macros by transcoder Signed-off-by:
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Madhav Chauhan authored
This patch select input PIPE for DSI, data lanes width, enable port sync mode and wait for DSI link to become ready. v2 by Jani: - Use MISSING_CASE with fallthrough instead of DRM_ERROR - minor stylistic changes Signed-off-by:
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Madhav Chauhan authored
This patch defines TRANS_DDI_FUNC_CTL and TRANS_DDI_FUNC_CTL2 registers and their bitfields for DSI. These registers are used for enabling port sync mode, input pipe select, data lane width configuration etc. v2: Changes: - Remove redundant extra line - Correct some of bitfield definition v3 by Jani: - Move DSI transcoder offsets to GEN11_FEATURES Signed-off-by: -
Michal Wajdeczko authored
We wrongly assumed that GuC is only using last scratch register for G2H messages, but in fact it is also using register [14] to report sleep state status. Remove that register from our H2G send registers pool. v2: No message from host to GuC uses more than 8 registers and the GuC FW itself uses an 8-element array to store the H2G message, so we may reduce our send array to just 8 registers (Daniele) v3: use explicit define (Daniele) v4: and explicit comment (Daniele) Signed-off-by:
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Madhav Chauhan authored
This patch programs DSI operation mode, pixel format, BGR info, link calibration etc for the DSI transcoder. This patch also extract BGR info of the DSI panel from VBT and save it inside struct intel_dsi which used for configuring DSI transcoder. v2: Rebase v3: Use newly defined bitfields. v4 by Jani: - Use intel_dsi_bitrate() - Make bgr_enabled bool - Use 0 instead of 0x0 - Replace DRM_ERROR() with MISSING_CASE() on pixel format and video mode - Use is_vid_mode() Signed-off-by:
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Madhav Chauhan authored
This patch defines transcoder function configuration registers and its bitfields for both DSI ports. Used while programming/enabling DSI transcoder. v2: Changes (Jani N) - Define _SHIFT and _MASK for bitfields - Define values for fields already shifted in place v3 by Jani: - Fix _SHIFT fields copy-pasted from _MASK - Indentation fixes - Reduce S3D orientation to single macro - Wrap a macro parameter in parens Signed-off-by: -
Madhav Chauhan authored
This patch adds _MMIO_DSI macros for accessing DSI transcoder registers. v2: Use _MMIO_TRANS() (Ville) Credits-to: Jani N Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by:
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Madhav Chauhan authored
This patch adds a helper function to retrieve DSI transcoder for a given DSI port using newly defined enum names for DSI transcoders. Signed-off-by:
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Madhav Chauhan authored
This patch programs D-PHY timing parameters for the bus turn around flow(in escape clocks) only if dsi link frequency <=800 MHz using DPHY_TA_TIMING_PARAM and its identical register DSI_TA_TIMING_PARAM (inside DSI Controller within the Display Core). v2: Changes - Don't use KHz() macro (Ville/Jani N) - Use newly defined bitfields v3 by Jani: - Use intel_dsi_bitrate() in favor of a new field - Remove redundant parens Signed-off-by: -
Madhav Chauhan authored
This patch programs D-PHY timing parameters for the clock and data lane (in escape clocks) of DSI controller (DSI port 0 and 1). These programmed timings would be used by DSI Controller to calculate link transition latencies of the data and clock lanes. v2: Use newly defined bitfields for data and clock lane v3 by Jani: - Rebase on dphy abstraction - Reduce local variables - Remove unrelated comment changes (Ville) - Use the same style for range checks as VLV (Ville) - Assign, don't OR dphy_reg contents Signed-off-by:
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Madhav Chauhan authored
This patch moves couple of legacy DSI functions to header and common DSI files so that they can be re-used by Gen11 DSI. No functional change. v2 by Jani: - Move intel_dsi_msleep() to intel_dsi_vbt.c Signed-off-by:
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Jani Nikula authored
Will be needed in the future. No functional changes. Cc: Madhav Chauhan <madhav.chauhan@intel.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Reviewed-by:
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- 19 Oct, 2018 1 commit
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Xiong Zhang authored
Currently the guest couldn't boot up under GVT-g environment as the following call trace exists: [ 272.504762] BUG: unable to handle kernel NULL pointer dereference at 0000000000000100 [ 272.504834] Call Trace: [ 272.504852] execlists_context_pin+0x2b2/0x520 [i915] [ 272.504869] intel_gvt_scan_and_shadow_workload+0x50/0x4d0 [i915] [ 272.504887] intel_vgpu_create_workload+0x3e2/0x570 [i915] [ 272.504901] intel_vgpu_submit_execlist+0xc0/0x2a0 [i915] [ 272.504916] elsp_mmio_write+0xc7/0x130 [i915] [ 272.504930] intel_vgpu_mmio_reg_rw+0x24a/0x4c0 [i915] [ 272.504944] intel_vgpu_emulate_mmio_write+0xac/0x240 [i915] [ 272.504947] intel_vgpu_rw+0x22d/0x270 [kvmgt] [ 272.504949] intel_vgpu_write+0x164/0x1f0 [kvmgt] GVT GEM context is created by i915_gem_context_create_gvt() which doesn't allocate ppgtt. So GVT GEM context structure doesn't have a valid i915_hw_ppgtt. This patch create ppgtt table at GVT GEM context creation, then assign shadow ppgtt's root table address to this ppgtt when shadow ppgtt will be used on GPU. So GVT GEM context has valid ppgtt address. But note that this ppgtt only contain valid ppgtt root table address, the table entry in this ppgtt structure are invalid. Fixes:4a3d3f67("drm/i915: Match code to comment and enforce ppgtt for execlists") Signed-off-by:
Xiong Zhang <xiong.y.zhang@intel.com> Reviewed-by:
Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by:
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- 18 Oct, 2018 9 commits
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Ville Syrjälä authored
Replace the kvmalloc_array() with i915_gem_object_get_dma_address() when populating rotated vmas. One random access mechanism ought to be enough for everyone? To calculate the size of the radix tree I think we can do something like this (assuming 64bit pointers): num_pages = obj_size / 4096 tree_height = ceil(log64(num_pages)) num_nodes = sum(64^n, n, 0, tree_height-1) tree_size = num_nodes * 576 If we compare that with the object size we should get a relative overhead of around .2% to 1% for reasonable sized objects, which framebuffers tend to be. Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Suggested-by:
Tvrtko Ursulin <tvrtko.ursulin@intel.com>
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Joonas Lahtinen authored
Use single exit point to drop rpm wakeref in case of an error. Fixes: 9d3eb2c3 ("drm/i915: Hold rpm wakeref for debugfs/i915_drop_caches_set") Signed-off-by:
Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
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Daniele Ceraolo Spurio authored
The test requires driver tweaks to avoid causing error messages on intentionally-triggered errors and to stop accessing non existing register. However, this is a pure GuC FW interface test and should be covered by FW validation, so it isn't really worth tweaking the driver for it and we're better off dropping it instead. Testing the driver running out of doorbells is already covered by igt_guc_doorbells Suggested-by:
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Jani Nikula authored
intel_dsi_vbt_init() has grown too unwieldy, and it's about to be modified due to ICL DSI. Abstract out the VLV specific dphy param init. No functional changes. Intentionally no stylistic changes during code movement. Cc: Madhav Chauhan <madhav.chauhan@intel.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Reviewed-by:
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Jani Nikula authored
Abstract bitrate calculation to a newly resurrected intel_dsi.c file that will contain common code for VLV and ICL DSI. No functional changes. Cc: Madhav Chauhan <madhav.chauhan@intel.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Reviewed-by:
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Jani Nikula authored
Encoders are not alike, make enable and disable hooks optional like other hooks. Utilize this in DSI code, and remove the silly nop hook. v2: Add the check also to intel_sanitize_encoder() (Madhav) Reviewed-by:
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Jani Nikula authored
Pass the type we want to simplify. No functional changes. v2: s/dev_priv/i915/g (Chris) Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by:
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Michal Wajdeczko authored
In response for I915_PARAM_HAS_HUC we are returning value that indicates if HuC firmware was loaded and verified. However, our previously used positive value was based on specific register bit which is about to change on future platform. Let's normalize our return values to 0 and 1 before clients will start to use Gen9 value. v2: use bool for implicit conversion (Chris) Signed-off-by:
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Tvrtko Ursulin authored
GEM_WARN_ON currently has dangerous semantics where it is completely compiled out on !GEM_DEBUG builds. This can leave users who expect it to be more like a WARN_ON, just without a warning in non-debug builds, in complete ignorance. Another gotcha with it is that it cannot be used as a statement. Which is again different from a standard kernel WARN_ON. This patch fixes both problems by making it behave as one would expect. It can now be used both as an expression and as statement, and also the condition evaluates properly in all builds - code under the conditional will therefore not unexpectedly disappear. To satisfy call sites which really want the code under the conditional to completely disappear, we add GEM_DEBUG_WARN_ON and convert some of the callers to it. This one can also be used as both expression and statement. >From the above it follows GEM_DEBUG_WARN_ON should be used in situations where we are certain the condition will be hit during development, but at a place in code where error can be handled to the benefit of not crashing the machine. GEM_WARN_ON on the other hand should be used where condition may happen in production and we just want to distinguish the level of debugging output emitted between the production and debug build. v2: * Dropped BUG_ON hunk. Signed-off-by:
Tomasz Lis <tomasz.lis@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181012063142.16080-1-tvrtko.ursulin@linux.intel.com
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