- 30 Mar, 2017 40 commits
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Andrey Grodzovsky authored
Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com> Reviewed-by: Ken Wang <Qingqing.Wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Huang Rui authored
This patch introduces a new flag named "amdgpu_firmware_load_type" to handle different firmware loading method. Since Vega10, there are three ways to load firmware. It would be better to use a flag and a fw_load_type kernel parameter to configure it. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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ken authored
Signed-off-by: ken <Qingqing.Wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Ken Wang authored
Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Ken Wang <Qingqing.Wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Ken Wang authored
These are used by various IP modules. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Ken Wang <Qingqing.Wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Felix Kuehling authored
This header defines the gfx v9 MEC structures. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Shaoyun Liu <Shaoyun.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
These are the Video Compression Engine registers for vega10. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
These are the Unifed Video Decoder registers for vega10. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
These are the THerMal control registers for vega10. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
These are the System Managment Unit IO registers for vega10. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
These are the System DMA register headers for vega10. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
These are the OS Services register headers for vega10. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
These are the Bus IO registers for vega10. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
These are the Bus InterFace registers for vega10. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
MP is the system management controller on vega10. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Add the MultiMedia Hub registers for vega10. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
These are the Host Data Path registers for vega10. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Add the Graphics Core register headers for vega10. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
These are the register headers for the Display and Composition Engine on vega10. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
ATHUB is part of the memory controller on soc15 asics. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
This adds the register bitfield enums for vega10. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
This header defines the IP layout for soc15 based SoCs. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
This adds basic support for asics that use atomfirmware.h to define their vbios tables. v2: rebase v3: squash in num scratch reg fix Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Ken Wang <Qingqing.Wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
There will be a slightly different version for atomfirmware. Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Ken Wang <Qingqing.Wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Supposedly atomfirmware rom header is 3.3 atombios is 1.1. v2: rebased on newer kernel Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
soc15 asics have a new vbios interface. These headers define that interface. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Nicolai Hähnle authored
We will add the fence to freed buffer objects in a later commit, to ensure that the underlying memory can only be re-used after all references in page tables have been cleared. Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Eric Huang authored
Power containment will degrade performance in some compute tests. Restore disabling it as before code refining in powerplay. v2: only in the compute profile Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
The ring structure already has what we need. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Avoids passing around additional parameters during setup. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Everything we need is in the ring structure. No need to pass all the bits explicitly. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
It's required. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
No need to loop through the compute queues twice. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
If KIQ isn't working, the compute rings won't work either. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
It's required. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
To better match where they are used. Called from sw_init and sw_fini. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Rex Zhu authored
load mc ucode in driver if VBIOS not loaded a full version of MC ucode, Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: jimqu <Jim.Qu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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