- 17 May, 2018 15 commits
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Feifei Xu authored
Initial powerplay support the same as vega10 for now. Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Feifei Xu <Feifei.Xu@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Feifei Xu authored
Reviewed-by:
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Feifei Xu authored
Reviewed-by:
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Feifei Xu authored
vega20_gpu_info firmware stores gpu configuration for vega20. v2: drop gpu info firmware for vega20 Squash of: drm/amdgpu: Add gpu_info firmware for vega20. drm/amdgpu: drop gpu_info firmware for vega20 Reviewed-by:
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Feifei Xu authored
Add vega20 to amd_asic_type enum and amdgpu_asic_name[]. Reviewed-by:
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James Zhu authored
Vega20 uses vce 4.1 engine, all the registers have the same absolute offset with vce 4.0. By adjusting vega20 VCE_BASE, vce 4.1 can reuse vce 4.0 header files. Signed-off-by:
James Zhu <James.Zhu@amd.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Feifei Xu authored
This headerfile contains vega20's ip base addresses. v2: squash in MP1_BASE fix Acked-by:
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Feifei Xu authored
In gmc_v9_0_vram_gtt_location(),the vram_base_offset is hardcoded to 0 in dGPU. Fix it by reading mmMC_VM_FB_OFFSET or return zfb_phys_addr if ZFB is enabled. Signed-off-by:
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Feifei Xu authored
Signed-off-by:
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Evan Quan authored
configuration change settings Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
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Evan Quan authored
This is needed for vega12 and vega20 which do not support legacy powerstate. With this new framework, the DAL clocks limits can also be honored on these asics. Signed-off-by:
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Feifei Xu authored
Update golden_settings_gc_9_0[]. Signed-off-by:
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Laurent Pinchart authored
Commit 75a07f39 ("drm: rcar-du: Zero-out sg_tables when duplicating plane state") introduced a reference to the alpha field of struct rcar_du_vsp_plane_state that got removed in commit 301a9b8d ("drm/rcar-du: Convert to the new generic alpha property"). The issue stems from the merge of the two commits through separate branches and breaks compilation of the driver. Fix it. Fixes: 75a07f39 ("drm: rcar-du: Zero-out sg_tables when duplicating plane state") Signed-off-by:
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by:
Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Tested-by:
Dave Airlie <airlied@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180515174752.28954-1-laurent.pinchart+renesas@ideasonboard.com
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Laurent Pinchart authored
The rcar_du_of_init() function is supposed to be defined as a stub when CONFIG_DRM_RCAR_LVDS is disabled as the rcar_du_of.c file isn't compiled in that case. However, a bug in the configuration option check makes it a stub when CONFIG_DRM_RCAR_LVDS=m as well, which prevents legacy DTs from being fixed at boot time. Fix the configuration option check by using IS_ENABLED. Fixes: 81c0e3dd ("drm: rcar-du: Fix legacy DT to create LVDS encoder nodes") Signed-off-by:
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Stephen Rothwell authored
Fixes: 5ae0283e ("drm/amdgpu: Add userptr support for KFD" Cc: Felix Kuehling <Felix.Kuehling@amd.com> Cc: Oded Gabbay <oded.gabbay@gmail.com> Signed-off-by:
Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by:
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- 15 May, 2018 25 commits
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git://people.freedesktop.org/~agd5f/linuxDave Airlie authored
Main changes for 4.18. I'd like to do a separate pull for vega20 later this week or next. Highlights: - Reserve pre-OS scanout buffer during init for seemless transition from console to driver - VEGAM support - Improved GPU scheduler documentation - Initial gfxoff support for raven - SR-IOV fixes - Default to non-AGP on PowerPC for radeon - Fine grained clock voltage control for vega10 - Power profiles for vega10 - Further clean up of powerplay/driver interface - Underlay fixes - Display link bw updates - Gamma fixes - Scatter/Gather display support on CZ/ST - Misc bug fixes and clean ups [airlied: fixup v3d vs scheduler API change] Link: https://patchwork.freedesktop.org/patch/msgid/20180515185450.1113-1-alexander.deucher@amd.comSigned-off-by:
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git://anongit.freedesktop.org/drm/drm-intelDave Airlie authored
Last drm/i915 changes for v4.18: - NV12 enabling (Chandra, Maarten) - ICL workarounds (Oscar) - ICL basic DPLL enabling (Paulo) - GVT updates - DP link config refactoring (Jani) - Module parameter to override DMC firmware (Jani) - PSR updates (José, DK, Daniel, Ville) - ICL DP vswing programming (Manasi) - ICL DBuf slice updates (Mahesh) - Selftest fixes and updates (Chris, Matthew, Oscar) - Execlist fixes and updates (Chris) - Stolen memory first 4k fix (Hans de Goede) - wait_for fixes (Mika) - Tons of GEM improvements (Chris) - Plenty of other fixes and improvements (Everyone) - Crappy changelog (Me) Signed-off-by:
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Nayan Deshmukh authored
this patch also effect the amdgpu and etnaviv drivers which use the function drm_sched_entity_init Signed-off-by:
Nayan Deshmukh <nayan26deshmukh@gmail.com> Suggested-by:
Lucas Stach <l.stach@pengutronix.de> Reviewed-by:
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Dirk Hohndel authored
This is dual licensed under GPL-2.0 or MIT. Signed-off-by:
Dirk Hohndel (VMware) <dirk@hohndel.org> Signed-off-by:
Thomas Hellstrom <thellstrom@vmware.com> Acked-by:
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Christian König authored
Quite useful to know. Signed-off-by:
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Christian König authored
It is meaningless anyway. v2: remove unused variable (Alex) Signed-off-by:
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Yong Zhao authored
This change prepares for a workaround in amdkfd for a GFX9 HW bug. It requires the control stack memory of compute queues, which is allocated from the second page of MQD gart BOs, to have mtype NC, rather than the default UC. Signed-off-by:
Yong Zhao <yong.zhao@amd.com> Reviewed-by:
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Mikita Lipski authored
Functionality to message smc to enable pwe after gpu suspense. It is used in case when display resumes from S3 and wants to start audio driver by enabling pwe. Signed-off-by:
Mikita Lipski <mikita.lipski@amd.com> Acked-by:
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Shirish S authored
This patch is in continuation to the "843e3c7d drm/amd/display: defer modeset check in dm_update_planes_state" where we started to eliminate the dependency on DRM_MODE_ATOMIC_ALLOW_MODESET to be set by the user space, which as such is not mandatory. After deferring, this patch eliminates the dependency on the flag for overlay planes. This has to be done in stages as its a pretty complex and requires thorough testing before we free primary planes as well from dependency on modeset flag. V2: Simplified the plane type check. Signed-off-by:
Shirish S <shirish.s@amd.com> Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Junwei Zhang authored
fix crash in trace. Signed-off-by:
Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by:
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Alex Deucher authored
These got moved to the new df module so no longer used in this file. Reviewed-by:
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Christian König authored
The UVD firmware doesn't seem to like the HDP flush here. This worked for years without HDP flush, so just skip it. Signed-off-by:
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Junwei Zhang authored
Signed-off-by:
David Zhou <david1.zhou@amd.com> Reviewed-by:
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Junwei Zhang authored
Then priority could be set before initialization. By default, it requires to kzalloc ttm bo. In fact, we always do so. Signed-off-by:
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Rex Zhu authored
The performance drop if the default TDP more than 256 Watt Reviewed-by:
Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
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Rex Zhu authored
under manual dpm mode, user can set gfx/mem clock through sysfs pp_dpm_sclk/mclk on Rv. Reviewed-by:
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Junwei Zhang authored
Used for working around an audio bug on some platforms. Signed-off-by:
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Colin Ian King authored
The declaration of pointer amdgpu_crtc has a redundant assignment to amdgpu_crtc. Clean this up by removing it. Detected by CoverityScan, CID#1460299 ("Evaluation order violation") Reviewed-by:Colin Ian King <colin.king@canonical.com> Signed-off-by:
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Colin Ian King authored
Trivial fix to spelling mistake in PP_ASSERT_WITH_CODE message text Signed-off-by:
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Rex Zhu authored
In order to keep consist with Vega, the output format of the pp_power_profile_mode would be <integer><mode name string>< “*” for current profile>:"detail settings" and remove the "CURRENT" mode line. for example: NUM MODE_NAME SCLK_UP_HYST SCLK_DOWN_HYST SCLK_ACTIVE_LEVEL MCLK_UP_HYST MCLK_DOWN_HYST MCLK_ACTIVE_LEVEL 0 3D_FULL_SCREEN: 0 100 30 0 100 10 1 POWER_SAVING: 10 0 30 - - - 2 VIDEO: - - - 10 16 31 3 VR: 0 11 50 0 100 10 4 COMPUTE: 0 5 30 - - - 5 CUSTOM *: 0 5 30 0 100 10 NUM MODE_NAME SCLK_UP_HYST SCLK_DOWN_HYST SCLK_ACTIVE_LEVEL MCLK_UP_HYST MCLK_DOWN_HYST MCLK_ACTIVE_LEVEL 0 3D_FULL_SCREEN: 0 100 30 0 100 10 1 POWER_SAVING *: 10 0 30 0 100 10 2 VIDEO: - - - 10 16 31 3 VR: 0 11 50 0 100 10 4 COMPUTE: 0 5 30 - - - 5 CUSTOM: - - - - - - Reviewed-by:
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Chunming Zhou authored
Shadow BO is located on GTT and its parent (PT and PD) BO could located on VRAM. In some case, the BO on GTT could be evicted but the parent did not. This may cause the shadow BO not be put in the evict list and could not be invalidate correctly. v2: suggested by Christian Signed-off-by:
Shaoyun Liu <Shaoyun.Liu@amd.com> Reviewed-by:
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Chunming Zhou authored
Signed-off-by:
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Tom St Denis authored
Signed-off-by:
Tom St Denis <tom.stdenis@amd.com> Reviewed-by:
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Tom St Denis authored
The callback .emit_reg_write_reg_wait was missing for vcn decode which resulted in a kernel oops. Signed-off-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by:
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Rex Zhu authored
with dpm enabled, need to get active crtcs in dc/no-dc mode. caused by 'commit ebb649667a31 ("drm/amdgpu: Set pm_display_cfg in non-dc mode")' Reviewed-by:
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